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PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
4583 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0009-0300Z Rev.3.00 2004.08.06
DESCRIPTION
The 4583 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with four 8-bit timers (each timer has one or two reload registers), a 10bit A/D converter, interrupts, and oscillation circuit switch function. The various microcomputers in the 4583 Group include variations of the built-in memory type as shown in the table below.
FEATURES
qMinimum instruction execution time .................................. 0.5 s (at 6 MHz oscillation frequency, in XIN through-mode) qSupply voltage Mask ROM version ...................................................... 1.8 to 5.5 V One Time PROM version ............................................. 2.5 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) qTimers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 3 ................................. 8-bit timer with two reload registers ROM (PROM) size ( 10 bits) 16384 words 16384 words
qInterrupt ........................................................................ 7 sources qKey-on wakeup function pins ................................................... 10 q A/D converter .......... 10-bit successive comparison method, 2ch qVoltage drop detection circuit Reset occurrence .................................... Typ. 1.5 V (Ta = 25 C) Reset release .......................................... Typ. 1.6 V (Ta = 25 C) qWatchdog timer qClock generating circuit (ceramic resonator/RC oscillation/quartz-crystal oscillation/onchip oscillator) qLED drive directly enabled (port D)
APPLICATION
Remote control transmitter
Part number M34583MD-XXXFP M34583EDFP (Note)
Note: Shipped in blank.
RAM size ( 4 bits) 384 words 384 words
Package 32P6U-A 32P6U-A
ROM type Mask ROM One Time PROM
PIN CONFIGURATION
P31/INT1
17 16 15 14
P61/AIN1
19
24
23
22
21
20
18
P03 P10 P11 P12 P13 D0 D1 D2
P60/AIN0
P02
P01
P00
P63
P62
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
P30/INT0 VDCE VDD VSS XIN XOUT CNVSS RESET
M34583MD-XXXFP M34583EDFP
13 12 11 10 9
D6/CNTR0
C/CNTR1
P20
P21
OUTLINE 32P6U-A
Pin configuration (top view) (4583 Group)
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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P22
D3
D4
D5
4583 Group
4 4 3
2
4
Block diagram (4583 Group)
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
I/O port
Port P0 Port P1 Port P3 Port P6 Port P2 System clock generation circuit XIN -XOUT (Ceramic/Quartz-crystal/RC) On-chip oscillator
Internal peripheral functions
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Timer
Timer 1(8 bits) Timer 2(8 bits) Timer 3(8 bits) Timer 4(8 bits)
Voltage drop detection circuit
Watchdog timer (16 bits)
A/D converter (10 bits 2 ch)
Memory
ROM
16384 words 10 bits
4500 series CPU core
ALU(4 bits)
Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
RAM
384 words 4 bits
Port C 1
Port D 7
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
PERFORMANCE OVERVIEW
Function 149 0.5 s (at 6.0 MHz oscillation frequency, in XIN through-mode) 16384 words 10 bits 384 words 4 bits Seven independent I/O ports; Port D6 is also used as CNTR0, respectively. The output structure is switched by software. 4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; a pull-up function, a key-on wakeup function and output structure can be switched P10-P13 I/O by software. 3-bit I/O port P20-P22 I/O 2-bit I/O port ; ports P30 and P31 are also used as INT0 and INT1, respectively. P30, P31 I/O 4-bit I/O port ; ports P60, P61 are also used as AIN0, AIN1, respectively. P60-P63 I/O 8-bit timer with a reload register is also used as an event counter. Timer 1 Timers Also, this is equipped with a period/pulse width measurement function. 8-bit timer with a reload register. Timer 2 8-bit timer with a reload register is also used as an event counter. Timer 3 8-bit timer with two reload registers and PWM output function. Timer 4 10-bit wide 2 ch, This is equipped with an 8-bit comparator function. A/D converter 7 (two for external, four for timer, one for A/D) Sources Interrupt 1 level Nesting 8 levels Subroutine nesting CMOS silicon gate Device structure 32-pin plastic molded LQFP (32P6U-A) Package -20 C to 85 C Operating temperature range 1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.) Supply voltage Mask ROM version One Time PROM version 2.5 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.) 2.8 mA (Ta=25C, VDD=5V, f(XIN)=6 MHz, f(STCK)=f(XIN), on-chip oscillator stop) Active mode Power 70 A (Ta=25C, VDD=5V, f(XIN)=32 kHz, f(STCK)=f(XIN), on-chip oscillator stop) dissipation 150 A (Ta=25C, VDD=5V, on-chip oscillator is used, f(STCK)=f(RING), f(XIN) stop) (typical value) 0.1 A (Ta=25C, VDD = 5 V, output transistors in the cut-off state) RAM back-up mode Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM RAM I/O (Input is Input/Output D0-D6 examined by ports skip decision) P00-P03 I/O
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
PIN DESCRIPTION
Pin VDD VSS CNVSS VDCE Name Power supply Ground CNVSS Voltage drop detection circuit enable Reset input/output Input/Output -- -- -- Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. This pin is used to operate/stop the voltage drop detection circuit. When "H" level is input to this pin, the circuit starts operating. When "L" level is input to this pin, the circuit stops operating. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs "L" level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. When using a 32 kHz quartz-crystal oscillator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port D6 is also used as CNTR0 pin. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 3-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to "1". Port P3 serves as a 2-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to "1". Ports P30 and P31 are also used as INT0 pin and INT1 pin, respectively. Port P6 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain. For input use, set the latch of the specified bit to "1". Ports P60, P61 are also used as AIN0, AIN1, respectively. Port C serves as a 1-bit port. The output structure is CMOS. For input use, set the latch of the specified bit to "1". Port C is also used as CNTR1. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to input the clock for the timer 3 event counter, and to output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also used as Ports D6 and C, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as Ports P30 and P31, respectively. A/D converter analog input pins. AIN0 pin and AIN1 pin are also used as Ports P60 and P61, respectively.
RESET
I/O
XIN XOUT D0-D6
Main clock input Main clock output I/O port D Input is examined by skip decision. I/O port P0
Input Output I/O
P00-P03
I/O
P10-P13
I/O port P1
I/O
P20-P23 P30, P31
I/O port P2 I/O port P3
I/O I/O
P60-P63
I/O port P6
I/O
C CNTR0, CNTR1
Output port C Timer input/output
Output I/O
INT0, INT1
Interrupt input
Input
AIN0, AIN1
Analog input
Input
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MULTIFUNCTION
Pin D6 C P30 P31 Multifunction CNTR0 CNTR1 INT0 INT1 Pin CNTR0 CNTR1 INT0 INT1 Multifunction D6 C P30 P31 Pin P60 P61 Multifunction AIN0 AIN1 Pin AIN0 AIN1 Multifunction P60 P61
Notes 1: Pins except above have just single function. 2: The input/output of P30 and P31 can be used even when INT0 and INT1 are selected. 3: The input/output of D6 can be used even when CNTR0 (input) is selected. 4: The input of D6 can be used even when CNTR0 (output) is selected. 5: The "H" output of C can be used even when CNTR1 (output) is selected.
DEFINITION OF CLOCK AND CYCLE
q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. * Clock (f(XIN)) by the external ceramic resonator * Clock (f(XIN)) by the external RC oscillation * Clock (f(XIN)) by the external input * Clock (f(RING)) of the on-chip oscillator which is the internal oscillator * Clock (f(XIN)) by the external quartz-crystal oscillation Table Selection of system clock Register MR System clock MR3 MR2 MR1 MR0 0 0 0 0 f(STCK) = f(XIN) 1 f(STCK) = f(RING) 0 1 0 0 f(STCK) = f(XIN)/2 1 f(STCK) = f(RING)/2 1 0 0 0 f(STCK) = f(XIN)/4 1 f(STCK) = f(RING)/4 1 1 0 0 f(STCK) = f(XIN)/8 1 f(STCK) = f(RING)/8 : 0 or 1 Note: The f(RING)/8 is selected after system is released from reset. When on-chip oscillator clock is selected for main clock, set the on-chip oscillator to be operating state.
q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. q Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode XIN through mode Ring through mode XIN divided by 2 mode Ring divided by 2 mode XIN divided by 4 mode Ring divided by 4 mode XIN divided by 8 mode Ring divided by 8 mode
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
PORT FUNCTION
Port Port D Pin D0-D5 D6/CNTR0 P00-P03 Input Output I/O (7) I/O (4) Output structure N-channel open-drain/ CMOS N-channel open-drain/ CMOS I/O unit 1 Control instructions SD, RD SZD CLD OP0A IAP0 Control registers FR1, FR2 W6 FR0 PU0 K0, K1 FR0 PU1 K0 Remark Output structure selection function (programmable) Built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions Built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions
Port P0
4
Port P1
P10-P13
I/O (4)
N-channel open-drain/ CMOS
4
OP1A IAP1
Port P2 Port P3 Port P6 Port C
P20, P21, P22 P30/INT0, P31/INT1 P60/AIN0, P61/AIN1, P62, P63 C/CNTR1
I/O (3) I/O (2) I/O (4) Output (1)
N-channel open-drain N-channel open-drain N-channel open-drain CMOS
3 2 4 1
OP2A IAP2 OP3A IAP3 OP6A IAP6 SCP RCP
I1, I2 K2 Q2 Q1 W4
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
CONNECTIONS OF UNUSED PINS
Pin XIN XOUT Open. Open. Connection Usage condition Internal oscillator is selected. Internal oscillator is selected. RC oscillator is selected. External clock input is selected for main clock. N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. CNTR1 input is not selected for timer 3 count source. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. The key-on wakeup function is not selected. N-channel open-drain is selected for the output structure. The pull-up function is not selected. The key-on wakeup function is not selected. (Note 1) (Note 1) (Note 2) (Note 3) (Note 4) (Note 4) (Note 6) (Note 5) (Note 4) (Note 6) (Note 7) (Note 5) (Note 4) (Note 7)
D0-D5 D6/CNTR0 C/CNTR1 P00-P03
Open. Connect to VSS. Open. Connect to VSS. Open. Open. Connect to VSS.
P10-P13
Open. Connect to VSS.
Open. Connect to VSS. Open. P21 Connect to VSS. Open. P22 Connect to VSS. Open. P30/INT0 Connect to Vss. Open. P31/INT1 Connect to Vss. Open. P32, P33 Connect to Vss. P60/AIN0, P61/AIN1 Open. Connect to Vss. P62, P63 P20
"0" is set to output latch. "0" is set to output latch.
Notes 1: After system is released from reset, the internal oscillation (on-chip oscillator) is selected for system clock (RG0=0, MR0=1). 2: When the CRCK instruction is executed, the RC oscillation circuit becomes valid. Be careful that the swich of system clock is not executed at oscillation start only by the CRCK instruction execution. In order to start oscillation, setting the main clock f(XIN) oscillation to be valid (MR1=0) is required. (If necessary, generate the oscillation stabilizing wait time by software.) Also, when the main clock (f(XIN)) is selected as system clock, set the main clock f(XIN) oscillation (MR1=0) to be valid, and select main clock f(XIN) (MR0=0). Be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started. 3: In order to use the external clock input for the main clock f(XIN), select the ceramic resonance by executing the CMCK instruction at the beggining of software, and then set the main clock (f(XIN)) oscillation to be valid (MR1=0). Until the main clock (f(XIN)) oscillation becomes valid (MR1=0) after ceramic resonance becomes valid, XIN pin is fixed to "H". When an external clock is used, insert a 1 k resistor to XIN pin in series for limits of current. 4: Be sure to select the output structure of ports D0-D5 and the pull-up function of P00-P03 and P10-P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00-P03 and P10-P13 with every two ports. If only one of the two pins is used, leave another one open. 6: The key-on wakeup function is selected with every two bits. When only one of key-on wakeup function is used, considering that the value of key-on wake-up control register K1, set the unused 1-bit to "H" input (turn pull-up transistor ON and open) or "L" input (connect to VSS, or open and set the output latch to "0"). 7: The key-on wakeup function is selected with every two bits. When one of key-on wakeup function is used, turn pull-up transistor of unused one ON and open. (Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
PORT BLOCK DIAGRAMS
Skip decision Register Y Decoder SZD instruction (Note 3) FR1i (Note 1) S SD instruction RD instruction RQ D0--D3 (Note 2) (Note 1)
CLD instruction
Skip decision Register Y Decoder SZD instruction FR20 (Note 1) S SD instruction RD instruction RQ D4 (Note 1) (Note 2)
CLD instruction
Skip decision Register Y Decoder SZD instruction FR21 (Note 1) S SD instruction RD instruction RQ D5 (Note 1) (Note 2)
CLD instruction
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3.
Port block diagram (1)
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Register Y
Decoder SZD instruction CLD instruction
Skip decision
FR22 S W60 RQ W23 1/2 1/2
0 1 0 1
(Note 1) D6/CNTR0 (Note 2)
SD instruction RD instruction Timer 1 underflow signal Timer 2 underflow signal
W62 Clock (input) for timer 1 event count or period measurement signal input
0 1
W10 W11 W50 W51
Clock (input) for timer 3 event count Timer 3 underflow signal W61 T R Q (Note 1) C/CNTR1 (Note 2) (Note 3) (Note 1) D
W32 PWMOD SCP instruction RCP instruction S R Q W30 W31
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: When CNTR1 input is selected, output transistor is turned OFF.
Port block diagram (2)
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(Note 3) IAP0 instruction Register A Aj FR00 Aj OP0A instruction K11 Key-on wakeup
0 1
Pull-up transistor
PU0j (Note 3)
(Note 1) P00, P01(Note 2) (Note 1)
D TQ K10
Level detection circuit Edge detection circuit (Note 4) IAP0 instruction Register A Ak
0 1
K00
FR01 Ak OP0A instruction K13 Key-on wakeup
0 1
Pull-up transistor
PU0k (Note 4)
(Note 1) P02, P03(Note 2) (Note 1)
D TQ K12
Level detection circuit Edge detection circuit (Note 3) IAP1 instruction Register A Aj
0 1
K01
FR02 Aj OP1A instruction Key-on wakeup D TQ
Pull-up transistor
PU1j (Note 3)
(Note 1) P10, P11(Note 2) (Note 1)
Level detection circuit
K02
(Note 4) IAP1 instruction Register A Ak FR03 Ak OP1A instruction Key-on wakeup D TQ
Pull-up transistor
PU1k (Note 4)
(Note 1) P12, P13(Note 2) (Note 1)
Level detection circuit
K03
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3.
Port block diagram (3)
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Register A A0
IAP2 instruction (Note 1) P20 (Note 2)
A0 OP2A instruction
DQ T
Register A A1
IAP2 instruction (Note 1) P21 (Note 2)
A1 OP2A instruction
DQ T
Register A A2
IAP2 instruction (Note 1) P22 (Note 2)
A2 OP2A instruction
DQ T
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.
Port block diagram (4)
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Register A A0
IAP3 instruction (Note 1) P30/INT0 (Note 2)
A0 OP3A instruction
DQ T (Note 3) External 0 interrupt circuit
External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input Period measurement circuit input
Register A A1
IAP3 instruction (Note 1) P31/INT1 (Note 2)
A1 OP3A instruction
DQ T (Note 3) External 1 interrupt circuit
External 1 interrupt Key-on wakeup input Timer 3 count start synchronous circuit input
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: As for details, refer to the external interrupt circuit structure.
Port block diagram (5)
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(Note 3) Register A Aj Q2j (Note 3) Aj OP6A instruction DQ T Q1 Decoder Analog input IAP6 instruction (Note 1) P60/AIN0, P61/AIN1 (Note 2)
(Note 4) Register A Ak IAP6 instruction (Note 1) P62, P63 Ak OP6A instruction DQ T (Note 2)
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3.
Port block diagram (6)
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(Note 1) P30/INT0
I12
Falling
0 1
Rising
One-sided edge detection circuit
I11
0
EXF0 Both edges detection circuit (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit
1
External 0 interrupt
Period measurement circuit input Timer 1 count start synchronous circuit Key-on wakeup
1
I13
K21
0
Skip decision (SNZI0 instruction)
I22 (Note 1) P31/INT1
1
Rising Falling
0
One-sided edge detection circuit
I21
0
EXF1 Both edges detection circuit (Note 2) Level detection circuit K22 (Note 3) Edge detection circuit Skip decision (SNZI1 instruction)
1
External 1 interrupt
I23
Timer 3 count start synchronous circuit K23
0
Key-on wakeup
1
This symbol represents a parasitic diode on the port. Notes 1: 2: I12 (I22) = 0: "L" level detected I12 (I22) = 1: "H" level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected
Port block diagram (7)
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
FUNCTION BLOCK OPERATIONS CPU
(CY)

(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation.
(M(DP)) Addition (A) ALU
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction.

Fig. 1 AMC instruction execution example
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B
TAB instruction
Register A
B3 B2 B1 B0
A3 A2 A1 A0
(4) Register D
Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed. Also, when the TABP p instruction is executed, the high-order 2 bits of the reference data in ROM is stored to the low-order 2 bits of register D, and the contents of the high-order 1 bit of register D is "0". (Figure 4). Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A
TBA instruction
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address
ROM 8 4 0
PCH p6 p5 p4 p3 p2 p1 p0
PCL DR2 DR1DR0 A3 A2 A1 A0
Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) High-order 2 bits Register D (3) High-order 1 bit of register D is "0".
Immediate field value p
The contents of The contents of register D register A
Fig. 4 TABP p instruction execution example
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call.
Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7
Stack pointer (SP) points "7" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.
(SP) 0 (SK0) 000116 (PC) SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.
(PC) (SK0) (SP) 7
Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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Notice: This is not a final specification. Some parametric limits are subject to change.
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM.
Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers.
Register Y (4)
Specifying RAM digit
Register X (4)
Specifying RAM file
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D3 D2 D1 D0
0
0
0
1
1 Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
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Notice: This is not a final specification. Some parametric limits are subject to change.
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34583MD/ED. Table 1 ROM size and pages Part number M34583MD M34583ED ROM (PROM) size ( 10 bits) 16384 words 16384 words Pages 128 (0 to 127) 128 (0 to 127)
987 000016 007F16 008016 00FF16 010016 017F16 018016
654
321
0 Page 0
Interrupt address page Subroutine special page
Page 1 Page 2 Page 3
Note: Data in pages 64 to 127 can be referred with the TABP p instruction after the SBK instruction is executed. Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed. A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 9 to 0) of all addresses can be used as data areas with the TABP p instruction.
3FFF16
Page 127
Fig. 10 ROM map of M34583MD/ED
9 008016 008216 008416 008616 008816 008A16 008C16
876543210 External 0 interrupt address External 1 interrupt address Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address Timer 4 interrupt address A/D interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). Table 2 shows the RAM size. Figure 12 shows the RAM map. * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers.
Table 2 RAM size Part number M34583MD/ED RAM size 384 words 4 bits (1536 bits)
RAM 384 words 4 bits (1536 bits)
Register Z Register X
0
1
0 ... 6 7 23
1 ... ... 15 0 ... ... 567
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 384 words
M34583MD/ED
Z=0, X=0 to 15 Z=1, X=0 to 7
Fig. 12 RAM map
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Register Y
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PRELIMINARY
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Notice: This is not a final specification. Some parametric limits are subject to change.
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)
Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 5 6 7 External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A/D interrupt
Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 4 underflow Completion of A/D conversion
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed.
Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function.
Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A/D interrupt Interrupt request flag EXF0 EXF1 T1F T2F T3F T4F ADF Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD Interrupt enable bit V10 V11 V12 V13 V20 V21 V22
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.
Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Enabled 1 Disabled 0
Skip instruction Invalid Valid
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Notice: This is not a final specification. Some parametric limits are subject to change.
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).
* Program counter (PC) ............................................................... Each interrupt address * Stack register (SK) The address of main routine to be .................................................................................................... executed when returning * Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 * Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)
Activated condition INT0 pin interrupt waveform input
Request flag Enable bit (state retained)
Enable flag
EXF0
V10
Address 0 in page 1 Address 2 in page 1
INT1 pin interrupt waveform input
EXF1
V11
Main routine Interrupt service routine
Interrupt occurs
Timer 1 underflow
T1F
V12
Address 4 in page 1
Timer 2 underflow Timer 3 underflow
T2F
V13
Address 6 in page 1
* * * *
T3F
V20
Address 8 in page 1 Address A in page 1
EI RTI
Interrupt is enabled
Timer 4 underflow A/D conversion completed
T4F
V21
ADF
V22
INTE
Address C in page 1
: Interrupt enabled state : Interrupt disabled state
Fig. 13 Program example of interrupt processing
Fig. 15 Interrupt system diagram
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Notice: This is not a final specification. Some parametric limits are subject to change.
(6) Interrupt control registers
* Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. * Interrupt control register V2 The timer 3, timer 4 and A/D interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A
Interrupt control register V2 V23 V22 V21 V20 Not used A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
This bit has no function, but read/write is enabled. Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid)
Note: "R" represents read enabled, and "W" represents write enabled.
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10-V13, V20-V23), and interrupt request flag are "1." The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).
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T3 T1 T1 T1 T2 T3 T2 T3 T2 T3 T1 T2 Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 1, 2) The program starts from the interrupt address.
Fig. 16 Interrupt sequence
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
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1 machine cycle
T1
T2
System clock (STCK)
EI instruction execution cycle
Interrupt enable flag (INTE)
INT0,INT1
External interrupt
EXF0,EXF1
Timer 1, Timer 2, Timer 3, Timer 4, and A-D interrupts
T1F,T2F,T3F,T4F, ADF
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
EXTERNAL INTERRUPTS
The 4583 Group has the external 0 interrupt and external 1 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin P30/INT0 Activated condition When the next waveform is input to P30/INT0 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms External 1 interrupt P31/INT1 When the next waveform is input to P31/INT1 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms I21 I22 Valid waveform selection bit I11 I12
(Note 1) P30/INT0
I12
Falling
0 1
Rising
One-sided edge detection circuit
I11
0
EXF0 Both edges detection circuit (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit
1
External 0 interrupt
I13
Period measurement circuit input Timer 1 count start synchronous circuit K21
0
Key-on wakeup
1
Skip decision (SNZI0 instruction)
I22 (Note 1) P31/INT1
1
Rising Falling
0
One-sided edge detection circuit
I21
0
EXF1 Both edges detection circuit (Note 2) Level detection circuit K22 (Note 3) Edge detection circuit Skip decision (SNZI1 instruction)
1
External 1 interrupt
I23
Timer 3 count start synchronous circuit K23
0
Key-on wakeup
1
This symbol represents a parasitic diode on the port. Notes 1: 2: I12 (I22) = 0: "L" level detected I12 (I22) = 1: "H" level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
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PRELIMINARY
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Notice: This is not a final specification. Some parametric limits are subject to change.
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. Set the bit 3 of register I1 to "1" for the INT0 pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs.
(2) External 1 interrupt request flag (EXF1)
External 1 interrupt request flag (EXF1) is set to "1" when a valid waveform is input to P31/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. Set the bit 3 of register I2 to "1" for the INT1 pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I2. Clear the EXF1 flag to "0" with the SNZ1 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. Set both the external 1 interrupt enable bit (V11) and the INTE flag to "1." The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31/INT1 pin, the EXF1 flag is set to "1" and the external 1 interrupt occurs.
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(3) External interrupt control registers
* Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Interrupt control register I1 I13 INT0 pin input control bit 0 1 0 1 0 1 0 1
* Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A.
at reset : 00002
at RAM back-up : state retained
R/W TAI1/TI1A
INT0 pin input disabled INT0 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected
I12
Interrupt valid waveform for INT0 pin/ return level selection bit
I11 I10
INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit
Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W TAI2/TI2A
INT1 pin input disabled INT1 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI1 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(4) Notes on External 0 interrupt
Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 18 ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 18 ). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18 ).
Note on bit 2 of register I1 When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 20) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 20). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT0 pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 18 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes. * When the input of INT0 pin is disabled (register I13 = "0"), set the key-on wakeup function to be invalid (register K20 = "0") before system enters to the RAM back-up mode. (refer to Figure 19).
: these bits are not used here. Fig. 20 External 0 interrupt program example-3
LA 0 TK2A DI EPOF POF
***
; (02) ; Input of INT0 key-on wakeup invalid ..
; RAM back-up
: these bits are not used here. Fig. 19 External 0 interrupt program example-2
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***
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(5) Notes on External 1 interrupt
Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. * Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 21) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 21). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 21).
Note on bit 2 of register I2 When the interrupt valid waveform of the P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. * Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 23) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 23). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 23).
***
LA 4 TV1A LA 8 TI2A NOP SNZ1 NOP
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Control of INT1 pin input is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI2A NOP SNZ1 NOP
***
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 21 External 1 interrupt program example-1 Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to "0" , the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes. * When the input of INT1 pin is disabled (register I23 = "0"), set the key-on wakeup function to be invalid (register K22 = "0") before system enters to the RAM back-up mode. (refer to Figure 22).
: these bits are not used here. Fig. 23 External 1 interrupt program example-3
LA 0 TK2A DI EPOF POF
***
; (02) ; Input of INT1 key-on wakeup invalid ..
; RAM back-up
: these bits are not used here. Fig. 22 External 1 interrupt program example-2
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Notice: This is not a final specification. Some parametric limits are subject to change.
TIMERS
The 4583 Group has the following timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
* Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse.
FF16 n : Counter initial value Count starts n Reload Reload
The contents of counter
1st underflow
2nd underflow
0016 Time n+1 count Timer interrupt "1" "0" request flag An interrupt occurs or a skip instruction is executed. n+1 count
Fig. 24 Auto-reload function The 4583 Group timer consists of the following circuits. * Prescaler : 8-bit programmable timer * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer * Timer 3 : 8-bit programmable timer * Timer 4 : 8-bit programmable timer * Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, 3, and 4 have the interrupt function, respectively) Prescaler and timers 1, 2, 3, and 4 can be controlled with the timer control registers PA, W1 to W6. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Table 9 Function related timers Circuit Prescaler Timer 1 Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT0 input) (period/pulse width measurement function) Timer 2 8-bit programmable binary down counter * System clock (STCK) * Prescaler output (ORCLK) * Timer 1 underflow (T1UDF) * PWM output (PWMOUT) Timer 3 8-bit programmable binary down counter (link to INT1 input) * PWM output (PWMOUT) * Prescaler output (ORCLK) * Timer 2 underflow (T2UDF) * CNTR1 input Timer 4 8-bit programmable binary down counter Watchdog timer * XIN input * Prescaler output (ORCLK) 65534 1 to 256 * Timer 2, 3 count source * CNTR1 output * Timer 4 interrupt * System reset (count twice) * WDF flag decision W4 1 to 256 * CNTR1 output control * Timer 3 interrupt W3 1 to 256 * Timer 3 count source * CNTR0 output * Timer 2 interrupt W2 Count source * Instruction clock (INSTCK) * Instruction clock (INSTCK) * Prescaler output (ORCLK) * XIN input * CNTR0 input Frequency dividing ratio 1 to 256 1 to 256 Use of output signal * Timer 1, 2, 3, amd 4 count sources * Timer 2 count source * CNTR0 output * Timer 1 interrupt Control register PA W1 W2 W5
(PWM output function) * Instruction clock (INSTCK) 16-bit fixed dividing frequency
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Division circuit Divided by 8 On-chip oscillator Ceramic resonance 1 Multiplexer (CMCK, CRCK, CYCK) (Note 1) 0 MR0 Divided by 4 Divided by 2
MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3)
System clock (STCK)
Instruction clock (INSTCK)
XIN
RC oscillation Quartz-crystal oscillation
PA0
Prescaler (8)
ORCLK
Reload register RPS (8) (TPSAB) (TABPS) W60 0 1 1 (TPSAB) (TPSAB) (TABPS)
Register B
Register A
Port D6 output
W23 0
1/2 1/2 00 01 10 11
T1UDF T2UDF
W51, W50
On-chip oscillator
W62 0 1 I12
1/16
D6/CNTR0
One-period generation circuit
W52
P30/INT0
I13 I10 W13
0 1
One-sided edge detection circuit
I11 0 (Note 2) 1
Both edges detection circuit
SQ R
W52 1 0
I10 1 0
T1UDF
W11, W10 (Note 3)
INSTCK ORCLK XIN
00 01 10 11 W12 W21, W20 00 01 10 11 W22 (TAB2) (TAB1)
W52 1
Timer 1 (8) Reload register R1 (8)
(T1AB) (TR1AB) (T1AB) (T1AB) (TAB1)
0
T1F
Timer 1 interrupt
Register B Register A
STCK ORCLK T1UDF PWMOUT
Timer 1 underflow signal (T1UDF)
Timer 2 (8) Reload register R2 (8)
(T2AB) (T2AB) (T2AB) (TAB2)
T2F
Timer 2 interrupt
Register B Register A
TR1AB: This instruction is used to transfer the contents of register A and register B to only reload register R1. PWMOUT: PWM output signal (from timer 4 output unit)
Timer 2 underflow signal (T2UDF)
Data is set automatically from each reload register when timer underflows (auto-reload function).
Notes 1: When CMCK instruction is executed, ceramic resonance is selected. When CRCK instruction is executed, RC oscillation is selected. When CYCK instruction is executed, quartz-crystal oscillator is selected. 2: Timer 1 count start synchronous circuit is set by the valid edge of P30/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: XIN cannot be used for the count source when bit 1 (MR1) of register MR is set to "1" and f(XIN) oscillation is stopped.
Fig. 25 Timer structure (1)
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Notice: This is not a final specification. Some parametric limits are subject to change.
I22
P31/INT1
I23 I20 W33
0 1
One-sided edge detection circuit
I21 0 1
Both edges detection circuit
(Note 4) SQ R
I20 1 0
T3UDF
W31, W30 00 01 10 11 W32 1 PWMOUT Port C output (TAB3)
PWMOUT ORCLK T2UDF
C/CNTR1 W63 0
Timer 3 (8) Reload register R3 (8)
(T3AB) (TR3AB) (T3AB) (T3AB) (TAB3)
T3F
Timer 3 interrupt
Register B Register A
Timer 3 underflow signal (T3UDF)
QD
W30 W31 W32
T3UDF W61
RT
Register B Register A
(T4HAB)
(Note 3)
XIN ORCLK 1/2 W40 0 1 W41
Reload register R4H (8) Reload control circuit
W42 1 0 (T4R4L)
TQ R
T4F
PWMOD W43 Timer 4 interrupt
Timer 4 (8)
"H" interval expansion
Reload register R4L (8)
(T4AB) (TAB4) (T4AB) (T4AB) (TAB4)
Register B Register A Watchdog timer
1 - - - - - - - - - - - - - - 16
INSTCK
(Note 5)
S Q
WDF1 WRST instruction RESET signal R S Q
(Note 7)
WEF D Q Watchdog reset signal
DWDT instruction R + (Note 6) WRST instruction
T
R
RESET signal
TR3AB: This instruction is used to transfer the contents of Notes 3: XIN cannot be used for the count source when bit 1 (MR1) of register A and register B to only reload register R3. register MR is set to "1" and f(XIN) oscillation is stopped. T4R4L: This instruction is used to transfer the contents of reload register R4L to timer 4. 4: Timer 3 count start synchronous circuit is set by the valid edge INSTCK: Instruction clock (system clock divided by 3) of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. ORCLK: Prescaler output (instruction clock divided by 1 to 256)
Data is set automatically from each reload register when timer underflows (auto-reload function).
5: Flag WDF1 is cleared to "0" and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = "1". The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = "0". 6: Flag WEF is cleared to "0" and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 7: The WEF flag is set to "1" at system reset or RAM back-up mode.
Fig. 26 Timer structure (2)
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Notice: This is not a final specification. Some parametric limits are subject to change.
Table 10 Timer related registers Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state initialized) Operating R/W TAW1/TW1A at RAM back-up : 02 W TPAA
Timer control register W1 W13 W12 W11 Timer 1 count source selection bits W10 Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit
at reset : 00002 0 1 0 1 W11 W10 0 0 0 1 1 0 1 1
at RAM back-up : state retained
Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) XIN input CNTR0 input R/W TAW2/TW2A
Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 CNTR0 output signal selection bit Timer 2 control bit
at reset : 00002 0 1 0 1 W21 W20 0 0 0 1 1 0 1 1
at RAM back-up : state retained
Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT)
Timer control register W3 W33 W32 W31 Timer 3 count source selection bits (Note 4) Timer 3 count auto-stop circuit selection bit (Note 3) Timer 3 control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
at RAM back-up : state retained
R/W TAW3/TW3A
W30
Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10="1"). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20="1"). 4: The port C output is invalid when CNTR1 output is selected for the timer 3 count source.
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Notice: This is not a final specification. Some parametric limits are subject to change.
Timer control register W4 W43 W42 W41 W40 CNTR1 pin output control bit PWM signal "H" interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
R/W TAW4/TW4A
CNTR1 output invalid CNTR1 output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2
Timer control register W5 W53 W52 W51 Signal for period measurement selection bits W50 Not used Period measurement circuit control bit
at reset : 00002 0 1 0 1 W51 W50 0 0 0 1 1 0 1 1
at RAM back-up : state retained
R/W TAW5/TW5A
This bit has no function, but read/write is enabled. Stop Operating Count source On-chip oscillator (f(RING/16)) CNTR0 pin input INT0 pin input Not available R/W TAW6/TW6A
Timer control register W6 W63 W62 W61 W60 CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D6/CNTR0 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D6 (I/O) / CNTR0 (input) CNTR0 (I/O) /D6 (input)
Note: "R" represents read enabled, and "W" represents write enabled.
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Notice: This is not a final specification. Some parametric limits are subject to change.
(1) Timer control registers
* Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. * Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the selection of CNTR0 output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. * Timer control register W3 Register W3 controls the selection of the count operation and count source of timer 3 count auto-stop circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. * Timer control register W4 Register W4 controls the CNTR1 output, the expansion of "H" interval of PWM output, and the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. * Timer control register W5 Register W5 controls the period measurement circuit and target signal for period measurement. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A. * Timer control register W6 Register W6 controls the count edges of CNTR0 pin and CNTR1 pin, selection of CNTR1 output auto-control circuit and the D6/ CNTR0 pin function. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A..
(2) Prescaler
Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; set data in prescaler, and set the bit 0 of register PA to "1." When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes "0"), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, 3, and 4 count sources.
(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; set data in timer 1 set count source by bits 0 and 1 of register W1, and set the bit 2 of register W1 to "1." When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to "1." Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to "1." Timer 1 underflow signal divided by 2 can be output from CNTR0 pin by clearing bit 3 of register W2 to "0" and setting bit 0 of register W6 to "1". The period measurement circuit starts operating by setting bit 2 of register W5 to "1" and timer 1 is used to count the one-period of the target signal for the period measurement. In this time, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement.
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Notice: This is not a final specification. Some parametric limits are subject to change.
(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; set data in timer 2, select the count source with the bits 0 and 1 of register W2, and set the bit 2 of register W2 to "1." When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2, and count continues (auto-reload function). Timer 2 underflow signal divided by 2 can be output from CNTR0 pin by setting bit 3 of register W2 to "1" and setting bit 0 of register W6 to "1".
(6) Timer 4 (interrupt function)
Timer 4 is an 8-bit binary down counter with two timer 4 reload registers (R4L, R4H). Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction. Data can be set in the reload register R4H with the T4HAB instruction. The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction. Data can be read from timer 4 with the TAB4 instruction. Stop counting and then execute the T4AB or TAB4 instruction to read or set timer 4 data. When executing the T4HAB instruction to set data to reload register R4H while timer 4 is operating, avoid a timing when timer 4 underflows. Timer 4 starts counting after the following process; set data in timer 4 set count source by bit 0 of register W4, and set the bit 1 of register W4 to "1." When a value set in reload register R4L is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes "0"), the timer 4 interrupt request flag (T4F) is set to "1," new data is loaded from reload register R4L, and count continues (auto-reload function). The PWM signal generated by timer 4 can be output from CNTR1 pin by setting bit 3 of the timer control register W4 to "1". Timer 4 can control the PWM output to CNTR1 pin with timer 3 by setting bit 1 of the timer control register W6 to "1".
(5) Timer 3 (interrupt function)
Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the TR3AB instruction to set data to reload register R3 while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; set data in timer 3 set count source by bits 0 and 1 of register W3, and set the bit 2 of register W3 to "1." When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes "0"), the timer 3 interrupt request flag (T3F) is set to "1," new data is loaded from reload register R3, and count continues (auto-reload function). INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 0 of register I2 to "1." Also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to "1."
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Notice: This is not a final specification. Some parametric limits are subject to change.
(7) Period measurement function (Timer 1, period measurement circuit)
Timer 1 has the period measurement circuit which performs timer count operation synchronizing with the one cycle of the signal divided by 16 of an on-chip oscillator, D6/CNTR0 pin input, or P30/ INT0 pin input (one cycle, "H", or "L" pulse width at the case of a P30/INT0 pin input). When the target signal for period measurement is set by bits 0 and 1 of register W5, a period measurement circuit is started by setting the bit 2 of register W5 to "1". Then, if a XIN input is set as the count source of a timer 1 and the bit 2 of register W1 is set to "1", timer 1 starts operation. Timer 1 starts operation synchronizing with the falling edge of the target signal for period measurement, and stops count operation synchronizing with the next falling edge (one-period generation circuit). When selecting D6/CNTR0 pin input as target signal for period measurement, the period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register W6 to "1". When selecting P30/INT0 pin input as target signal for period measurement, period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register I1 to "1". A timer 1 interrupt request flag (T1F) is set to "1" after completing measurement operation. When a period measurement circuit is set to be operating, timer 1 interrupt request flag (T1F) is not set by timer 1 underflow signal, but turns into a flag which detects the completion of period measurement. In addition, a timer 1 underflow signal can be used as timer 2 count source. Once period measurement operation is completed, even if period measurement valid edge is input next, timer 1 is in a stop state and measurement data is held. When a period measurement circuit is used again, stop a period measurement circuit at once by setting the bit 2 of register W5 to "0", and change a period measurement circuit into a state of operation by setting the bit 2 of register W5 to "1" again. When a period measurement circuit is used, clear bit 0 of register I1 to "0", and set a timer 1 count start synchronous circuit to be "not selected". Start timer operation immediately after operation of a period measurement circuit is started. When the target edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to "0" to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to "1" when the period measurement circuit is stopped by clearing bit 2 of register W5 to "0". In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to "0" (refer to Figure 27) and then, stop the bit 2 of register W5 to "0" to stop the period measurement circuit.
In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 27). Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 27).
LA 0 TV1A LA 0 TW5A NOP SNZT1 NOP
***
; (02) ; The SNZT1 instruction is valid ........ ; (02) ; Period measurement circuit stop ........................................................... ; The SNZT1 instruction is executed (T1F flag cleared) ...........................................................
: these bits are not used here. Fig. 27 Period measurement circuit program example When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the target signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.)
(8) Pulse width measurement function (timer 1, period measurement circuit)
A period measurement circuit can measure "H" pulse width (from rising to falling) or "L" pulse width (from falling to rising) of P30/ INT0 pin input (pulse width measurement function) when the following is set; * Set the bit 0 of register W5 to "0", and set a bit 1 to "1" (target for period measurement circuit: 30/INT0 pin input). * Set the bit 1 of register I1 to "1" (INT0 pin edge detection circuit: both edges detection) The measurement pulse width ("H" or "L") is decided by the period measurement circuit and the P30/INT0 pin input level at the start time of timer operation. At the time of the start of a period measurement circuit and timer operation, "L" pulse width (from falling to rising) when the input level of P30/INT0 pin is "H" or "H" pulse width (from rising to falling) when its level is "L" is measured. When the input of P30/INT0 pin is selected as the target for measurement, set the bit 3 of register I1 to "1", and set the input of INT0 pin to be enabled.
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Notice: This is not a final specification. Some parametric limits are subject to change.
(9) Count start synchronization circuit (timer 1, timer 3)
Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INT0 pin and INT1 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to "1" and the control by INT0 pin input can be performed. Timer 3 count start synchronous circuit function is selected by setting the bit 0 of register I2 to "1" and the control by INT1 pin input can be performed. When timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT0 pin or INT1 pin. The valid waveform of INT0 pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 or I20 to "0" or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow.
(11) Timer input/output pin (D6/CNTR0 pin, C/CNTR1 pin)
CNTR0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4. When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to "0". The D6/CNTR0 pin function can be selected by bit 0 of register W6. The selection of CNTR1 output signal can be controlled by bit 3 of register W4. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the rising or falling waveform of CNTR0 input. The count edge is selected by the bit 2 of register W6. When the CNTR1 input is selected for timer 3 count source, timer 3 counts the rising or falling waveform of CNTR1 input. The count edge is selected by the bit 3 of register W6. When CNTR1 input is selected, the output of port C is invalid (highimpedance).
(12) PWM output function (C/CNTR1, timer 3, timer 4)
When bit 3 of register W4 is set to "1", timer 4 reloads data from reload register R4L and R4H alternately each underflow. Timer 4 generates the PWM signal (PWMOUT) of the "L" interval set as reload register R4L, and the "H" interval set as reload register R4H. The PWM signal (PWMOUT) is output from CNTR1 pin. When bit 2 of register W4 is set to "1" at this time, the interval (PWM signal "H" interval) set to reload register R4H for the counter of timer 4 is extended for a half period of count source. In this case, when a value set in reload register R4H is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set "1" or more to reload register R4H. When bit 1 of register W6 is set to "1", the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 3 underflow. However, when timer 3 is stopped (bit 2 of register W3 is cleared to "0"), this function is canceled. Even when bit 1 of a register W4 is cleared to "0" in the "H" interval of PWM signal, timer 4 does not stop until it next timer 4 underflow. When clearing bit 1 of register W4 to "0" to stop timer 4 at the use of PWM output function, avoid a timing when timer 4 underflows.
(10) Count auto-stop circuit (timer 1, timer 3)
Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to "1". It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W3 to "1". It is cleared by the timer 3 underflow and the count source to timer 3 is stopped. This function is valid only when the timer 3 count start synchronous circuit is selected.
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Notice: This is not a final specification. Some parametric limits are subject to change.
(13) Timer interrupt request flags (T1F, T2F, T3F, T4F)
Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, SNZT4). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction. The timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement.
(14) Precautions
Note the following for the use of timers. * Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. * Timer count source Stop timer 1, 2, 3 and 4 counting to change its count source. * Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. * Writing to the timer Stop timer 1, 2, 3 or 4 counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB) to write its data. * Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. * Timer 4 Avoid a timing when timer 4 underflows to stop timer 4 at the use of PWM output function. When "H" interval extension function of the PWM signal is set to be "valid", set "1" or more to reload register R4H. * Timer input/output pin When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to "0".
* Period measurement function When a period measurement circuit is used, clear bit 0 of register I1 to "0", and set a timer 1 count start synchronous circuit to be "not selected". Start timer operation immediately after operation of a period measurement circuit is started. When the target edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to "0" to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to "1" when the period measurement circuit is stopped by clearing bit 2 of register W5 to "0". In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to "0" (refer to Figure 28) and then, stop the bit 2 of register W5 to "0" to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 28). Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 28).
LA 0 TV1A LA 0 TW5A NOP SNZT1 NOP
***
; (02) ; The SNZT1 instruction is valid ........ ; (02) ; Period measurement circuit stop ........................................................... ; The SNZT1 instruction is executed (T1F flag cleared) ...........................................................
: these bits are not used here. Fig. 28 Period measurement circuit program example While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the target signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P30/INT0 pin is selected for measurement, set the bit 3 of a register I1 to "1", and set the input of INT0 pin to be enabled.
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Notice: This is not a final specification. Some parametric limits are subject to change.
q CNTR1 output: invalid (W43 = "0")
Timer 4 count source 0316 (R4L) (R4L) (R4L) (R4L) (R4L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal (output invalid)
Timer 4 start
PWM signal "L" fixed
q CNTR1 output: valid (W43 = "1") PWM signal "H" interval extension function: invalid (W42 = "0")
Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal 3 clock Timer 4 start PWM period 7 clock 3 clock PWM period 7 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
q CNTR1 output: valid (W43 = "1") PWM signal "H" interval extension function: valid (W42 = "1") (Note)
Timer 4 count source Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal Timer 4 start 3.5 clock PWM period 7.5 clock 3.5 clock PWM period 7.5 clock 0316 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216
Note: At PWM signal "H" interval extension function: valid, set "0116" or more to reload register R4H.
Fig. 29 Timer 4 operation (reload register R4L: "0316", R4H: "0216")
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Notice: This is not a final specification. Some parametric limits are subject to change.
CNTR1 output auto-control circuit by timer 3 is selected.
q CNTR1 output: valid (W43 = "1") CNTR1 output auto-control circuit selected (W61 = "1") PWM signal Timer 3 underflow signal Timer 3 start CNTR1 output CNTR1 output start
q CNTR1 output auto-control function
PWM signal Timer 3 underflow signal Timer 3 start Register W61
Timer 3 stop
CNTR1 output CNTR1 output start CNTR1 output stop

When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid, the CNTR1 output invalid state is retained. When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid, the CNTR1 output valid state is retained. When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid.
Fig. 30 CNTR1 output auto-control function by timer 3
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Notice: This is not a final specification. Some parametric limits are subject to change.
qWaveform extension function of CNTR1 output "H" interval: Invalid (W42 = "0"), CNTR1 output: valid (W43 = "1"), Count source: XIN input selected (W40 = "0"), Reload register R4L: "0316" Reload register R4H: "0216"
Timer 4 count start timing
Machine cycle
Mi
Mi+1
Mi+2
System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal
TW4A instruction execution cycle (W41) 1
0316 (R4L)
0216 0116 0016 0216 0116 0016 0316 0216 0116 (R4H) (R4L)
Timer 4 count start timing
Timer 4 count stop timing
Machine cycle Mi Mi+1 Mi+2
System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) Timer 4 underflow signal PWM signal
TW4A instruction execution cycle (W41) 0
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R4H) (R4L)
0216 (R4H)
(Note 1)
Timer 4 count stop timing
Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = "1"), avoid a timing when timer 4 underflows. If these timings overlap, a hazard may occur in a CNTR1 output waveform. 2: At CNTR1 output valid, timer 4 stops after "H" interval of PWM signal set by reload register R4H is output.
Fig. 31 Timer 4 count start/stop timing
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Notice: This is not a final specification. Some parametric limits are subject to change.
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from "FFFF16" after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches "000016," the next count pulse is input), the WDF1 flag is set to "1." If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to "1" after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to "0" and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is "1", the WDF1 flag is cleared to "0" and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is "0", the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid.
FFFF16 Value of 16-bit timer (WDT) 000016 WDF1 flag
65534 count (Note) WDF2 flag
RESET pin output Reset released WRST instruction executed (skip executed) System reset
After system is released from reset (= after program is started), timer WDT starts count down. When timer WDT underflow occurs, WDF1 flag is set to "1." When the WRST instruction is executed, WDF1 flag is cleared to "0," the next instruction is skipped. When timer WDT underflow occurs while WDF1 flag is "1," WDF2 flag is set to "1" and the watchdog reset signal is output. The output transistor of RESET pin is turned "ON" by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock.
Fig. 32 Watchdog timer function
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Notice: This is not a final specification. Some parametric limits are subject to change.
When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 33). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 34). The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function.
WRST
***
; WDF1 flag cleared
DI DWDT WRST
***
; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared
Fig. 33 Program example to start/stop watchdog timer
WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF Oscillation stop
Fig. 34 Program example to enter the mode when using the watchdog timer
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***
***
***
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
A/D CONVERTER (Comparator)
The 4583 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Table 11 A/D converter characteristics Characteristics Parameter Conversion format Successive comparison method Resolution 10 bits Relative accuracy Linearity error: 2LSB (2.7 V VDD 5.5V) Differential non-linearity error: 0.9LSB (2.2 V VDD 5.5V) Conversion speed 31 s (f(XIN) = 6 MHz, STCK = f(XIN) (XIN through-mode), ADCK = INSTCK/6) Analog input pin 2
Register B (4)
Register A (4) 4 4 IAP6 (P60-P63) OP6A (P60-P63) TAQ1 TQ1A 4 TAQ2 TQ2A 4 TAQ3 TQ3A 2 TALA
Division circuit Divided by 48
4 4
4
Q13 Q12 Q11 Q10
Q23 Q22 Q21 Q20
Q33 Q32 Q31 Q30
8 TABAD
8 TADAB
Q31, Q30
11 10 01 00
Q32 3
Instruction clock On-chip oscillator 1 clock
0
Divided by 24 Divided by 12 Divided by 6
A/D conversion clock (ADCK)
Q13
0
2-channel multi-plexed analog switch
A/D control circuit
1
P60/AIN0 P61/AIN1
ADF (1)
A/D interrupt
1
Comparator
0
Q13 DAC operation signal
Successive comparison register (AD) (10) 10
0 1
Q13 10 8
0 1 1
Q13
8 DA converter
(Note 1)
8 VDD
8
VSS Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 35 A/D conversion circuit structure
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Notice: This is not a final specification. Some parametric limits are subject to change.
Table 12 A/D control registers
A/D control register Q1 Q13 Q12 Q11 Q10 A/D operation mode selection bit Not used Not used Analog input pin selection bits 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAQ1/TQ1A
A/D conversion mode Comparator mode This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. AIN0 AIN1 R/W TAQ2/TQ2A
A/D control register Q2 Q23 Q22 Q21 Q20 Not used Not used P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. P61 AIN1 P60 AIN0
A/D control register Q3 Q33 Q32 Q31 A/D converter operation clock division ratio selection bits Not used A/D converter operation clock selection bit 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W TAQ3/TQ3A
This bit has no function, but read/write is enabled.
Q30
Instruction clock (INSTCK) On-chip oscillator (f(RING)) Division ratio Q31 Q30 Frequency divided by 6 0 0 0 1 Frequency divided by 12 1 0 Frequency divided by 24 1 1 Frequency divided by 48
Note: "R" represents read enabled, and "W" represents write enabled.
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Notice: This is not a final specification. Some parametric limits are subject to change.
(1) A/D control register
* A/D control register Q1 Register Q1 controls the selection of A/D operation mode and the selection of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. * A/D control register Q2 Register Q2 controls the selection of P60/AIN0, P61/AIN1. Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of register Q2 to register A. * A/D control register Q3 Register Q3 controls the selection of A/D converter operation clock. Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of register Q3 to register A.
(4) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to "1" when A/D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
(5) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD.
(6) Operation description
A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: When the A/D conversion starts, the register AD is cleared to "00016." Next, the topmost bit of the register AD is set to "1," and the comparison voltage Vref is compared with the analog input voltage VIN. When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to "1." When the comparison result is Vref > VIN, it is cleared to "0." The 4583 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conversion stops after 2 machine cycles + A/D conversion clock (31 s when f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/ 6) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to "1" as soon as A/D conversion completes (Figure 36).
(2) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to "0."
(3) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref =
VDD n 1024
n: The value of register AD (n = 0 to 1023)
Table 13 Change of successive comparison register AD during A/D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes 1: 1st comparison result 3: 3rd comparison result 9: 9th comparison result Change of successive comparison register AD
-------------
Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD VDD 4

1 1 1
0 1 2
0 0 1
-----------------------------------------------------------------
0 0 0
0 0 0
0 0 0
---------

8 VDD 1024
A/D conversion result
-------------
1
2
3
-------------
-----
8
9
A
2
2: 2nd comparison result 8: 8th comparison result A: 10th comparison result
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Notice: This is not a final specification. Some parametric limits are subject to change.
(7) A/D conversion timing chart
Figure 36 shows the A/D conversion timing chart.
ADST instruction 2 machine cycles + 10/f(ADCK) A/D conversion completion flag (ADF) DAC operation signal
Fig. 36 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which the analog input from P60/AIN0 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. Instruction clock/6 is selected as the A/D converter operation clock. Select the AIN0 pin function with the bit 0 of the register Q2. Select the AIN0 pin function and A/D conversion mode with the register Q1. Also, the instruction clock divided by 6 is selected with the register Q3. (refer to Figure 37) Execute the ADST instruction and start A/D conversion. Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion. Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0).
(Bit 3)
(Bit 0)
1
A/D control register Q2
AIN0 pin function selected
(Bit 3)
(Bit 0)
0
0
0
0
A/D control register Q1
AIN0 pin selected A/D conversion mode
(Bit 3)
(Bit 0)
0
0
0
A/D control register Q3
Frequency divided by 6 Instruction clock : Set an arbitrary value.
Fig. 37 Setting registers
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Notice: This is not a final specification. Some parametric limits are subject to change.
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to "1." Below, the operation at comparator mode is described.
(12) Comparator operation start instruction (ADST instruction)
In comparator mode, executing ADST starts the comparator operating. The comparator stops 2 machine cycles + A/D conversion clock f(ADCK) 1 clock after it has started (4 s at f(XIN) = 6.0 MHz in XIN through mode, f(ADCK) = f(INSTCK)/6). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1."
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 n
(13) Notes for the use of A/D conversion
* TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0." * Operation mode of A/D converter Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. Clear the bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag.
n: The value of register AD (n = 0 to 255)
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1." The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
ADST instruction 2 machine cycles + 1/f(ADCK) Comparison result store flag(ADF) DAC operation signal
Comparator operation completed. (The value of ADF is determined)
Fig. 38 Comparator operation timing chart
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Notice: This is not a final specification. Some parametric limits are subject to change.
(14) Definition of A/D converter accuracy
The A/D conversion accuracy is defined below (refer to Figure 39). * Relative accuracy Zero transition voltage (V0T) This means an analog input voltage when the actual A/D conversion output data changes from "0" to "1." Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from "1023" to "1022." Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. * Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics.
Vn: Analog input voltage when the output data changes from "n" to "n+1" (n = 0 to 1022) * 1LSB at relative accuracy VFST-V0T (V) 1022 VDD 1024
* 1LSB at absolute accuracy
(V)
Output data
1023 1022
Full-scale transition voltage (VFST)
Differential non-linearity error = Linearity error = c a [LSB]
b-a a [LSB] b a
n+1 n
Actual A/D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1-Vn c: Difference between ideal Vn and actual Vn
Ideal line of A/D conversion between V0-V1022
1 0
V0 V1 Zero transition voltage (V0T)
Vn
Vn+1
V1022 Analog voltage
VDD
Fig. 39 Definition of A/D conversion accuracy
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Notice: This is not a final specification. Some parametric limits are subject to change.
RESET FUNCTION
System reset is performed by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when "H" level is applied to RESET pin, software starts from address 0 in page 0.
f(RING)
RESET On-chip oscillator (internal oscillator)
is counted 120 to 144 times.
Program starts (address 0 in page 0)
Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed.
Fig. 40 Reset release timing
Reset input
=
On-chip oscillator (internal oscillator) is
1 machine cycle or more
counted 120 to 144 times.
0.85VDD RESET 0.3VDD
Program starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 41 RESET pin input waveform and reset operation
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Notice: This is not a final specification. Some parametric limits are subject to change.
(1) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V until the value of supply voltage reaches the minimum operating voltage must be set to 100 s or less.
If the rising time exceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
100 s or less
VDD (Note 3)
Pull-up transistor
(Note 1) (Note 2)
Power-on reset circuit output
RESET pin
Internal reset signal Power-on reset circuit
(Note 1)
Voltage drop detection circuit Watchdog reset signal
WEF SRST instruction
Internal reset signal
Reset state Power-on Reset released
Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 42 Structure of reset pin and its peripherals, and power-on reset operation Table 14 Port state at reset Name D0-D5 D6/CNTR0 C/CNTR1 P00-P03 P10-P13 P20, P21, P22 P30/INT0, P31/INT1 P60/AIN0, P61/AIN1, P62, P63
Notes 1: Output latch is set to "1." 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF.
Function D0-D5 D6 C P00-P03 P10-P13 P20-P22 P30, P31 P60-P63 High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) "L" (VSS) level
State
High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Note 1) High-impedance (Note 1) High-impedance (Note 1)
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Notice: This is not a final specification. Some parametric limits are subject to change.
(2) Internal state at reset
Figure 43 and 44 show internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure are undefined, so set the initial value to them.
* Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) .................................................................................................. 0 * Power down flag (P) ............................................................................................................. 0 * External 0 interrupt request flag (EXF0) .............................................................................. 0 * External 1 interrupt request flag (EXF1) .............................................................................. 0 * Interrupt control register V1 .................................................................................................. 0 000 * Interrupt control register V2 .................................................................................................. 0 000 * Interrupt control register I1 ................................................................................................... 0 000 * Interrupt control register I2 ................................................................................................... 0 000 * Timer 1 interrupt request flag (T1F) ..................................................................................... 0 * Timer 2 interrupt request flag (T2F) ..................................................................................... 0 * Timer 3 interrupt request flag (T3F) ..................................................................................... 0 * Timer 4 interrupt request flag (T4F) ..................................................................................... 0 * Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 * Watchdog timer enable flag (WEF) ...................................................................................... 1 * Timer control register PA ...................................................................................................... 0 * Timer control register W1 ..................................................................................................... 0 000 * Timer control register W2 ..................................................................................................... 0 000 * Timer control register W3 ..................................................................................................... 0 000 * Timer control register W4 ..................................................................................................... 0 000 * Timer control register W5 ..................................................................................................... 0 000 * Timer control register W6 ..................................................................................................... 0 000 * Clock control register MR ..................................................................................................... 1 111 * Clock control register RG ..................................................................................................... 0 * 8-bit general register SI ........................................................................................................ * A/D conversion completion flag (ADF) ................................................................................. 0 * A/D control register Q1 ......................................................................................................... 0 000 * A/D control register Q2 ......................................................................................................... 0 000 * A/D control register Q3 ......................................................................................................... 0 000 * Successive comparison register AD .................................................................................... * Comparator register .............................................................................................................. * Key-on wakeup control register K0 ...................................................................................... 0 000 * Key-on wakeup control register K1 ...................................................................................... 0 000 * Key-on wakeup control register K2 ...................................................................................... 0 000 * Pull-up control register PU0 ................................................................................................. 0 000 * Pull-up control register PU1 ................................................................................................. 0 000
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled) (Interrupt disabled)
(Prescaler stopped) (Timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer 4 stopped) (Period measurement circuit stopped)
(On-chip oscillator operating)
"" represents undefined. Fig. 43 Internal state at reset 1
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* Port output structure control register FR0 ........................................................................... 0000 * Port output structure control register FR1 ........................................................................... 0000 * Port output structure control register FR2 ........................................................................... 0000 * Carry flag (CY) ...................................................................................................................... 0 * Register A ............................................................................................................................. 0000 * Register B ............................................................................................................................. 0000 * Register D ............................................................................................................................. * Register E ............................................................................................................................. * Register X ............................................................................................................................. 0000 * Register Y ............................................................................................................................. 0000 * Register Z ............................................................................................................................. * Stack pointer (SP) ................................................................................................................ 111 * Operation source clock .......................................................... On-chip oscillator (operating) * Ceramic resonator circuit .............................................................................................. Stop * RC oscillation circuit ...................................................................................................... Stop * Quartz-crystal oscillation circuit .................................................................................... Stop
"" represents undefined.
Fig. 44 Internal state at reset 2
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VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value.
(1) SVDE instruction When the SVDE instruction is executed, the voltage drop detection circuit is valid even after system enters into the RAM back-up mode. The SVDE instruction can be executed only once. In order to release the execution of the SVDE instruction, the system reset is required.
S EPOF instruction + POF instruction Internal reset signal Key-on wakeup signal
Q
R
Q
S R
SVDE instruction Internal reset signal VDCE
*
VRST + VRST -
- +
Voltage drop detection circuit Reset signal
Voltage drop detection circuit
Fig. 45 Voltage drop detection reset circuit
VDD
VRST (reset release voltage) VRST -(reset voltage)
+
Voltage drop detection circuit Reset signal Microcomupter starts operation after on-chip oscillator (internal oscillator) clock is counted 120 to 144 times. RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ).
Fig. 46 Voltage drop detection circuit operation waveform Table 15 Voltage drop detection circuit operation state VDCE pin "L" "H" At CPU operating Invalid Valid At RAM back-up (SVDE instruction not executed) Invalid Invalid At RAM back-up (SVDE instruction executed) Invalid Valid
VDD Recommended operatng condition min.value + VRST - VRST
(2) Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 47); supply voltage does not fall below to VRST-, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that.
No reset Program failure may occur.
VDD Recommended operatng condition min.value + VRST - VRST Reset
Normal operation
Fig. 47 VDD and VRST-
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RAM BACK-UP MODE
The 4583 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 16 shows the function and states retained at RAM back-up. Figure 47 shows the state transition.
Table 16 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1, I2 Selection of oscillation circuit Clock control register MR Timer 1 function Timer 2 function Timer 3 function Timer 4 function Watchdog timer function Timer control register PA, W4 Timer control registers W1 to W3, W5, W6 A/D conversion function A/D control registers Q1 to Q3 Voltage drop detection circuit Port level Key-on wakeup control register K0 to K2 Pull-up control registers PU0, PU1 Port output direction registers FR0 to FR2 External 0 interrupt request flag (EXF0) External 1 interrupt request flag (EXF1) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Timer 3 interrupt request flag (T3F) Timer 4 interrupt request flag (T4F) A/D conversion completion flag (ADF) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) RAM back-up O O O (Note 3) (Note 3) (Note 3) (Note 3) (Note 4) O O (Note 5) (Note 6) O O O (Note 3) (Note 3) (Note 3) (Note 3) (Note 4) (Note 4)
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the powerdown flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF and POF instructions continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is "1."
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0 when; * reset pulse is input to RESET pin, or * reset by watchdog timer is performed, or * voltage drop detection circuit detects the voltage drop, or * SRST instruction is executed. In this case, the P flag is "0."
Notes 1:"O" represents that the function can be retained, and "" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The voltage drop detection circuit is valid at RAM back-up when the SVDE instruction is executed while VDCE pin is "H". 6: In the RAM back-up mode, C/CNTR1 pin outputs "L" level. However, when the CNTR input is selected (W11, W10="11"), C/ CNTR1 pin is in an input enabled state (output=high-impedance). Other ports retain their respective output levels.
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(4) Return signal
An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 17 shows the return condition for each return source.
(5) Related registers
* Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K1 Register K1 controls the return condition and valid waveform/ level selection for port P0. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K1 to register A. * Key-on wakeup control register K2 Register K2 controls the INT0 and INT1 key-on wakeup functions and return condition function. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. Table 17 Return source and return condition Return source Return condition
* Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. * Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU0 to register A. * External interrupt control register I1 Register I1 controls the valid waveform of external 0 interrupt, input control of INT0 pin, and return input level. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. * External interrupt control register I2 Register I2 controls the valid waveform of external 1 interrupt, input control of INT1 pin, and return input level. Set the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Remarks
External wakeup signal
The key-on wakeup function can be selected with 2 port units. Select the return level ("L" level or "H" level), and return condition (return by level or edge) with the register K1 according to the external state before going into the RAM back-up state. Ports P10-P13 Return by an external "L" level in- The key-on wakeup function can be selected with 2 port units. Set the port using the key-on wakeup function to "H" level before going into the RAM put. back-up state. Ports P00-P03 Return by an external "H" level or "L" level input, or rising edge ("L""H") or falling edge ("H""L"). INT0 INT1 Return by an external "H" level or Select the return level ("L" level or "H" level) with the registers I1 and I2 ac"L" level input, or rising edge cording to the external state, and return condition (return by level or edge) ( " L " " H " ) o r f a l l i n g e d g e with the register K2 before going into the RAM back-up state. ("H""L"). The external interrupt request flags (EXF0, EXF1) are not set.
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Notice: This is not a final specification. Some parametric limits are subject to change.
A
Operation state Reset (Note 1) * Operation source clock: f(RING) * f(XIN): Stop MR11
(Note 5) Key-on wakeup
E
RAM back-up mode
POF instruction execution (Note 4)
(Note 2) MR10
B
Operation state * Operation source clock: f(RING) * f(XIN): Operating (Note 3) MR00 MR01 POF instruction execution (Note 4)
Operation state * Operation source clock: f(XIN) * f(RING): Operating RG00 RG01 POF instruction execution (Note 4)
C
D
Operation state * Operation source clock: f(XIN) * f(RING): Stop POF instruction execution (Note 4) f(RING): stop f(XIN): stop
Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times. 2: The f(XIN) oscillation circuit (ceramic resonance, RC oscillation or quartz-crystal oscillation) selected by the CMCK, CRCK or CYCK instruction starts oscillatng (the start of oscillation and the operation source clock is not switched by these instructions). The start/stop of oscillation and the operation source is switched by register MR. Surely, select the f(XIN) oscillation circuit by executing the CMCK, CRCK or CYCK instruction before clearing MR1 to "0". MR1 cannot be cleared to "0" when the oscillation circuit is not selected. 3: Generate the wait time by software until the oscillation is stabilized, and then, switch the system clock. 4: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state. 5: System returns to state A certainly when returning from the RAM back-up mode. However, the selected contents (CMCK, CRCK, CYCK instruction execution state) of f(XIN) oscillation circuit is retained.
Fig. 48 State transition
POF EPOF instruction + instruction Reset input
Power down flag P S Q
Program start Yes
R
P = "1" ? No
Warm start
q Set source
*******
EPOF instruction + POF instruction
Cold start
q Clear source * * * * * * Reset input
Fig. 49 Set source and clear source of the P flag Fig. 50 Start condition identified example using the SNZP instruction
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Table 18 Key-on wakeup control register, pull-up control register Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Key-on wakeup control register K1 K13 K12 K11 K10 Ports P02 and P03 return condition selection bit Ports P02 and P03 valid waveform/ level selection bit Ports P01 and P00 return condition selection bit Ports P01 and P00 valid waveform/ level selection bit Key-on wakeup control register K2 K23 K22 K21 K20 INT1 pin return condition selection bit INT1 pin key-on wakeup contro bit INT0 pin return condition selection bit INT0 pin key-on wakeup contro bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Return by level Return by edge Falling waveform/"L" level Rising waveform/"H" level Return by level Return by edge Falling waveform/"L" level Rising waveform/"H" level at reset : 00002 Return by level Return by edge Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used at RAM back-up : state retained R/W TAK2/TK2A at RAM back-up : state retained R/W TAK1/TK1A
Note: "R" represents read enabled, and "W" represents write enabled.
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Table 19 Key-on wakeup control register, pull-up control register Pull-up control register PU0 PU03 PU02 PU01 PU00 P03 pin pull-up transistor control bit P02 pin pull-up transistor control bit P01 pin pull-up transistor control bit P00 pin pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 P13 pin pull-up transistor control bit P12 pin pull-up transistor control bit P11 pin pull-up transistor control bit P10 pin pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained R/W TAPU1/ TPU1A at RAM back-up : state retained R/W TAPU0/ TPU0A
Note: "R" represents read enabled, and "W" represents write enabled.
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CLOCK CONTROL
The clock control circuit consists of the following circuits. * On-chip oscillator (internal oscillator) * Ceramic resonator * RC oscillation circuit * Quartz-crystal oscillation circuit * Multi-plexer (clock selection circuit) * Frequency divider * Internal clock generating circuit The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 51 shows the structure of the clock control circuit. The 4583 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator, the RC oscillation or quartz-crystal oscillator can be used for the main clock (f(XIN)) of the 4583 Group. The CMCK instruction, CRCK instruction or CYCK instruction is executed to select the ceramic resonator, RC oscillator or quartz-crystal oscillator respectively.
The CMCK, CRCK, and CYCK instructions can be used only to select main clock (f(XIN)). In this time, the start of oscillation and the switch of system clock are not performed. The oscillation start/stop of main clock f(XIN) is controlled by bit 1 of register MR. The system clock is selected by bit 0 of register MR. The oscillation start/stop of on-chip oscillator is controlled by register RG. The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. Execute the main clock (f(XIN)) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). When the CMCK, CRCK, and CYCK instructions are never executed, main clock (f(XIN)) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(XIN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(XIN)) selected for the system clock cannot be stopped.
Division circuit Divided by 8 MR0 1 RG0 0 Divided by 4 Divided by 2
MR3, MR2 11 10 01 00
System clock (STCK) Internal clock generating circuit (divided by 3)
On-chip oscillator (internal oscillator)
Instruction clock (INSTCK)
S XIN XOUT
Ceramic resonance
Multiplexer QS
RQ CMCK instruction
RC oscillation
R QS CRCK instruction
Quartz-crystal oscillation
R QS MR1 QS R EPOF instruction + R Internal reset signal Key-on wakeup signal POF instruction CYCK instruction
Fig. 51 Clock control circuit structure
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(1) Main clock generating circuit (f(XIN))
The ceramic resonator, RC oscillation or quartz-crystal oscillator can be used for the main clock of this MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscillator. When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK instruction. When the quartz-crystal oscillator is used, execute the CYCK instruction. The oscillation start/stop of main clock f(XIN) is controlled by bit 1 of register MR. The system clock is selected by bit 0 of register MR. The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. Execute the CMCK, CRCK or CYCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK, CRCK or CYCK instruction is not executed in program, this MCU operates by the on-chip oscillator.
Reset
On-chip oscillator operation
CMCK instruction
CRCKinstruction
CYCK instruction
* Main clock: ceramic resonance * On-chip oscillator: operating * System clock: on-chip oscillator clock
* Main clock: RC oscillation circuit * On-chip oscillator: operating * System clock: on-chip oscillator clock
* Main clock: Quartz-crystal circuit * On-chip oscillator: operating * System clock: on-chip oscillator clock
* Set the main clock (f(XIN)) oscillation by bit 1 of register MR. * Switch the system clock by bit 0 of register MR. Also, when system clock is switched after main clock oscillation is started, generate the oscillation stabilizing wait time by program if necessary. * Set the on-chip oscillator clock oscillation by register RG.
Fig. 52 Switch to ceramic resonance/RC oscillation/quartz-crystal oscillation
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(2) On-chip oscillator operation
When the MCU operates by the on-chip oscillator as the main clock (f(XIN)) without using the ceramic resonator, RC oscillator or quartz-crystal oscillation, leave XIN pin and XOUT pin open (Figure 53). The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products.
M34583
use the CMCK, CRCK * Do not instructions in program.and CYCK
XOUT Open
XIN Open
Fig. 53 Handling of XIN and XOUT when operating on-chip oscillator
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 54).
M34583
Execute the CMCK instruction in program.
XOUT
Note: Externally connect a damping resistor Rd depending on the oscillation frequency. Rd (A feedback resistor is built-in.) Use the resonator manufacturer's recommended value COUT because constants such as capacitance depend on the resonator.
XIN
*
CIN
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 55). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Fig. 54 Ceramic resonator external circuit
M34583
R
XIN
XOUT Open
* Execute the CRCK instruction in program.
(5) Quartz-crystal oscillator
When a quartz-crystal oscillator is used as the main clock (f(XIN)), connect this external circuit and a quartz-crystal oscillator to pins XIN and XOUT at the shortest distance. Then, execute the CYCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 56).
C
Fig. 55 External RC oscillation circuit
(6) External clock
When the external clock signal for the main clock (f(XIN)) is used, connect the clock source to XIN pin and XOUT pin open. In program, after the CMCK instruction is executed, set main clock (f(XIN)) oscillation start to be enabled (MR1=0). For this product, when RAM back-up mode and main clock (f(XIN)) stop (MR1=1), XIN pin is fixed to "H" in order to avoid the through current by floating of internal logic. The XIN pin is fixed to "H" until main clock (f(XIN)) oscillation starts to be valid (MR1=0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 k or more resistor to XIN pin in series to limit of current by competitive signal.
XIN
M34583
* Execute the CYCK instruction in program.
XOUT
Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Rd Use the quartz-crystal manufacturer's recommended value because constants such as caCOUT pacitance depend on the resonator.
CIN
Fig. 56 External quartz-crystal circuit
* Execute the CMCK instruction in program, and set the main clock
M34583
f(XIN) to be enabled (MR1=0)
XOUT VDD VSS
XIN
Open R 1k or more
External oscillation circuit Fig. 57 External clock input circuit
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(7) Clock control register MR
Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 20 Clock control registers Clock control register MR MR3 Operation mode selection bits MR2 MR1 MR0 Main clock f(XIN) oscillation circuit control bit System clock oscillation source selection bit
(8) Clock control register RG
Register RG controls start/stop of on-chip oscillator. Set the contents of this register through register A with the TRGA instruction.
at reset : 11112 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1
at RAM back-up : 11112
R/W TAMR/ TMRA
Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(XIN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) On-chip oscillator clock (f(RING)) W TRGA
Clock control register RG RG0 On-chip oscillator (f(RING)) control bit 0 1
at reset : 02
at RAM back-up : 02
On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop
Note: "R" represents read enabled, and "W" represents write enabled.
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/en/rom).
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LIST OF PRECAUTIONS
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k (connect this resistor to CNVSS/ VPP pin as close as possible). Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register Z (2 bits) * Register D (3 bits) * Register E (8 bits) Register initial values 2 The initial value of the following registers are undefined at RAM backup. After system is returned from RAM back-up, set initial values. * Register Z (2 bits) * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. Multifunction * The input/output of P30 and P31 can be used even when INT0 and INT1 are selected. * The input/output of D6 can be used even when CNTR0 (input) is selected. * The input of D6 can be used even when CNTR0 (output) is selected. * The "H" output of C can be used even when CNTR1 (output) is selected.
Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. Timer count source Stop timer 1, 2, 3 and 4 counting to change its count source. Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. Writing to the timer Stop timer 1, 2, 3 or 4 counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB) to write its data.
10
Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. Timer 4 Avoid a timing when timer 4 underflows to stop timer 4 at the use of PWM output function. When "H" interval extension function of the PWM signal is set to be "valid", set "1" or more to reload register R4H. Timer input/output pin When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to "0".
11
12
13
Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to "0" to stop the watchdog timer function. * The watchdog timer function is valid after system is returned from the RAM back-up state. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up state, and stop the watchdog timer function. * When the watchdog timer function and RAM back-up function are used at the same time, execute the WRST instruction before system enters into the RAM back-up state and initialize the flag WDF1.
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Notice: This is not a final specification. Some parametric limits are subject to change.
14
Period measurement circuit When a period measurement circuit is used, clear bit 0 of register I1 to "0", and set a timer 1 count start synchronous circuit to be "not selected". Start timer operation immediately after operation of a period measurement circuit is started. When the edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer operation becomes valid. Accordingly, be careful of count data. When data is read from timer, stop the timer and clear bit 2 of register W5 to "0" to stop the period measurement circuit, and then execute the data read instruction. Depending on the state of timer 1, the timer 1 interrupt request flag (T1F) may be set to "1" when the period measurement circuit is stopped by clearing bit 2 of register W5 to "0". In order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register V1 to "0" (refer to Figure 58) and then, stop the bit 2 of register W5 to "0" to stop the period measurement circuit. In addition, execute the SNZT1 instruction to clear the T1F flag after executing at least one instruction (refer to Figure 58). Also, set the NOP instruction for the case when a skip is performed with the SNZT1 instruction (refer to Figure 58). While a period measurement circuit is operating, the timer 1 interrupt request flag (T1F) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period measurement. When a period measurement circuit is used, select the sufficiently higher-speed frequency than the signal for measurement for the count source of a timer 1. When the signal for period measurement is D6/CNTR0 pin input, do not select D6/CNTR0 pin input as timer 1 count source. (The XIN input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P30/INT0 pin is selected for measurement, set the bit 3 of a register I1 to "1", and set the input of INT0 pin to be enabled.
LA 0 TV1A LA 0 TW5A NOP SNZT1 NOP
***
; (02) ; The SNZT1 instruction is valid ........ ; (02) ; Period measurement circuit stop ........................................................... ; The SNZT1 instruction is executed (T1F flag cleared) ...........................................................
: these bits are not used here. Fig. 58 Period measurement circuit program example
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15
P30/INT0 pin Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 59 ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 59 ). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 59 ).
Note on bit 2 of register I1 When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 61) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 61). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 61).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT0 pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... : these bits are not used here.
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
***
Fig. 59 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the RAM back-up mode is selected and the input of INT0 pin is disabled, be careful about the following notes. * When the input of INT0 pin is disabled (register I13 = "0"), set the key-on wakeup function to be invalid (register K20 = "0") before system enters to the RAM back-up mode. (refer to Figure 60).
: these bits are not used here. Fig. 61 External 0 interrupt program example-3
LA 0 TK2A DI EPOF POF
***
; (02) ; Input of INT0 key-on wakeup invalid ..
; RAM back-up
: these bits are not used here. Fig. 60 External 0 interrupt program example-2
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P31/INT1 pin Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes.
16
Note on bit 2 of register I2 When the interrupt valid waveform of the P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. * Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 64) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 64). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 64).
* Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 62) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 62). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 62).
***
LA 4 TV1A LA 8 TI2A NOP SNZ1 NOP
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Control of INT1 pin input is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI2A NOP SNZ1 NOP
***
; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 62 External 1 interrupt program example-1 Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared to "0", the RAM back-up mode is selected and the input of INT1 pin is disabled, be careful about the following notes. * When the input of INT1 pin is disabled (register I23 = "0"), set the key-on wakeup function to be invalid (register K22 = "0") before system enters to the RAM back-up mode. (refer to Figure 63).
: these bits are not used here. Fig. 64 External 1 interrupt program example-3
LA 0 TK2A DI EPOF POF
***
; (02) ; Input of INT1 key-on wakeup invalid ..
; RAM back-up
: these bits are not used here. Fig. 63 External 1 interrupt program example-2
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17 A/D converter-1 * When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0." * Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. * Clear the bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. * The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag.
19
POF instruction When the POF instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction continuously. Program counter Make sure that the PC does not specify after the last page of the built-in ROM. Power-on reset When the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 V to the value of supply voltage or more must be set to 100 s or less. If the rising time exceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage. Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 68); supply voltage does not fall below to VRST-, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that.
VDD Recommended operatng condition min.value + VRST - VRST
20
21
LA 8 TV2A LA 0 TQ1A
***
; (02) ; The SNZAD instruction is valid ........ ; (02) ; Operation mode of A/D converter is changed from comparator mode to A/D conversion mode.
22
SNZAD NOP
***
: these bits are not used here.
Fig. 65 A/D converter program example-3
18
A/D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins (Figure 66). When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 67. In addition, test the application products sufficiently.
Sensor
AIN
No reset Program failure may occur.
Apply the voltage withiin the specifications to an analog input pin.
Fig. 66 Analog input external circuit example-1
VDD Recommended operatng condition min.value + VRST - VRST Reset
Normal operation
Fig. 68 VDD and
About 1k
VRST-
Sensor
AIN
Fig. 67 Analog input external circuit example-2
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23
Clock control Execute the main clock (f(XIN)) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these instructions is valid. The CMCK, CRCK, and CYCK instructions can be used only to select main clock (f(XIN)). In this time, the start of oscillation and the switch of system clock are not performed. When the CMCK, CRCK, and CYCK instructions are never executed, main clock (f(XIN)) cannot be used and system can be operated only by on-chip oscillator. The no operated clock source (f(RING)) or (f(XIN)) cannot be used for the system clock. Also, the clock source (f(RING) or f(XIN)) selected for the system clock cannot be stopped. On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. When considering the oscillation stabilize wait time at the switch of clock, be careful that the variable frequency of the on-chip oscillator clock. External clock When the external clock signal for the main clock (f(XIN)) is used, connect the clock source to XIN pin and XOUT pin open. In program, after the CMCK instruction is executed, set main clock (f(XIN)) oscillation start to be enabled (MR1=0). For this product, when RAM back-up mode and main clock (f(XIN)) stop (MR1=1), XIN pin is fixed to "H" in order to avoid the through current by floating of internal logic. The XIN pin is fixed to "H" until main clock (f(XIN)) oscillation start to be valid (MR1=0) by the CMCK instruction from reset state. Accordingly, when an external clock is used, connect a 1 k or more resistor to XIN pin in series to limit of current by competitive signal. Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version.
27
Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
24
25
26
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CONTROL REGISTERS
Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A
Interrupt control register V2 V23 V22 V21 V20 Not used A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
This bit has no function, but read/write is enabled. Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) R/W TAI1/TI1A
Interrupt control register I1 I13 INT0 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
INT0 pin input disabled INT0 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected
I12
Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)
I11 I10
INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit
Interrupt control register I2 I23 INT1 pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W TAI2/TI2A
INT1 pin input disabled INT1 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI1 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected
I22
Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2)
I21 I20
INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to "1".
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Clock control register MR MR3 Operation mode selection bits MR2 MR1 MR0 Main clock f(XIN) oscillation circuit control bit System clock oscillation source selection bit
at reset : 11112 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1
at RAM back-up : 11112
R/W TAMR/ TMRA
Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(XIN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) On-chip oscillator clock (f(RING)) W TRGA
Clock control register RG RG0 On-chip oscillator (f(RING)) control bit 0 1
at reset : 02
at RAM back-up : 02
On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop W TPAA
Timer control register PA PA0 Prescaler control bit 0 1
at reset : 02 Stop (state initialized) Operating
at RAM back-up : 02
Timer control register W1 W13 W12 W11 Timer 1 count source selection bits W10 Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit
at reset : 00002 0 1 0 1 W11 W10 0 0 0 1 1 0 1 1
at RAM back-up : state retained
R/W TAW1/TW1A
Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source Instruction clock (INSTCK) Prescaler output (ORCLK) XIN input CNTR0 input R/W TAW2/TW2A
Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 CNTR0 output signal selection bit Timer 2 control bit
at reset : 00002 0 1 0 1 W21 W20 0 0 0 1 1 0 1 1
at RAM back-up : state retained
Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating Count source System clock (STCK) Prescaler output (ORCLK) Timer 1 underflow signal (T1UDF) PWM signal (PWMOUT)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10="1").
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Timer control register W3 W33 W32 W31 Timer 3 count source selection bits (Note 3) Timer 3 count auto-stop circuit selection bit (Note 2) Timer 3 control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 1 1 0 1 0 1
at RAM back-up : state retained
R/W TAW3/TW3A
W30
Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 2 underflow signal (T2UDF) CNTR1 input
Timer control register W4 W43 W42 W41 W40 CNTR1 pin function selection bit PWM signal "H" interval expansion function control bit Timer 4 control bit Timer 4 count source selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
R/W TAW4/TW4A
CNTR1 output invalid CNTR1 output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2
Timer control register W5 W53 W52 W51 Signal for period measurement selection bits W50 Not used Period measurement circuit control bit
at reset : 00002 0 1 0 1 W51 W50 0 0 0 1 1 0 1 1
at RAM back-up : state retained
R/W TAW5/TW5A
This bit has no function, but read/write is enabled. Stop Operating Count source On-chip oscillator (f(RING/16)) CNTR0 pin input INT0 pin input Not available R/W TAW6/TW6A
Timer control register W6 W63 W62 W61 W60 CNTR1 pin input count edge selection bit CNTR0 pin input count edge selection bit CNTR1 output auto-control circuit selection bit D6/CNTR0 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
Falling edge Rising edge Falling edge Rising edge CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D6 (I/O) / CNTR0 (input) CNTR0 (I/O) /D6 (input)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 3 count start synchronous circuit is selected (I20="1"). 3: The port C output is invalid when CNTR1 output is selected for the timer 3 count source.
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A/D control register Q1 Q13 Q12 Q11 Q10 A/D operation mode selection bit Not used Not used Analog input pin selection bits 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W TAQ1/TQ1A
A/D conversion mode Comparator mode This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. AIN0 AIN1 R/W TAQ2/TQ2A
A/D control register Q2 Q23 Q22 Q21 Q20 Not used Not used P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. P61 AIN1 P60 AIN0 R/W TAQ3/TQ3A
A/D control register Q3 Q33 Q32 Q31 A/D converter operation clock division ratio selection bits Not used A/D converter operation clock selection bit 0 1 0 1
at reset : 00002
at RAM back-up : state retained
This bit has no function, but read/write is enabled.
Q30
Instruction clock (INSTCK) On-chip oscillator (f(RING)) Division ratio Q31 Q30 0 0 Frequency divided by 6 0 1 Frequency divided by 12 1 0 Frequency divided by 24 1 1 Frequency divided by 48
Note: "R" represents read enabled, and "W" represents write enabled.
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Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit Key-on wakeup control register K1 K13 K12 K11 K10 Ports P02 and P03 return condition selection bit Ports P02 and P03 valid waveform/ level selection bit Ports P01 and P00 return condition selection bit Ports P01 and P00 valid waveform/ level selection bit Key-on wakeup control register K2 K23 K22 K21 K20 INT1 pin return condition selection bit INT1 pin key-on wakeup contro bit INT0 pin return condition selection bit INT0 pin key-on wakeup contro bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W TAK0/TK0A
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used at reset : 00002 Return by level Return by edge Falling waveform/"L" level Rising waveform/"H" level Return by level Return by edge Falling waveform/"L" level Rising waveform/"H" level at reset : 00002 Return by level Return by edge Key-on wakeup not used Key-on wakeup used Return by level Return by edge Key-on wakeup not used Key-on wakeup used at RAM back-up : state retained R/W TAK2/TK2A at RAM back-up : state retained R/W TAK1/TK1A
Note: "R" represents read enabled, and "W" represents write enabled.
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Pull-up control register PU0 PU03 PU02 PU01 PU00 P03 pin pull-up transistor control bit P02 pin pull-up transistor control bit P01 pin pull-up transistor control bit P00 pin pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 P13 pin pull-up transistor control bit P12 pin pull-up transistor control bit P11 pin pull-up transistor control bit P10 pin pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at RAM back-up : state retained
R/W TAPU0/ TPU0A
at RAM back-up : state retained
R/W TAPU1/ TPU1A
Note: "R" represents read enabled, and "W" represents write enabled.
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Port output structure control register FR0 FR03 FR02 FR01 FR00 Ports P12, P13 output structure selection bit Ports P10, P11 output structure selection bit Ports P02, P03 output structure selection bit Ports P00, P01 output structure selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
W TFR0A
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output at reset : 00002 at RAM back-up : state retained W TFR1A
Port output structure control register FR1 FR13 FR12 FR11 FR10 Port D3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit 0 1 0 1 0 1 0 1
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR2A
Port output structure control register FR2 FR23 FR22 FR21 FR20 Not used Port D6/CNTR0 output structure selection bit Port D5 output structure selection bit Port D4 output structure selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
This bit has no function, but write is enabled. N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output
8-bit general-purpose register SI
at reset : undefined
at RAM back-up : undefined
R/W
8-bit general purpose register. 8-bit data can be transferred between register A and register B with the TABSI and TSIAB instructions.
Note: "R" represents read enabled, and "W" represents write enabled.
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Notice: This is not a final specification. Some parametric limits are subject to change.
INSTRUCTIONS
The 4583 Group has the 149 instructions. Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table Symbol A B DR E V1 V2 I1 I2 MR RG PA W1 W2 W3 W4 W5 W6 Q1 Q2 Q3 PU0 PU1 FR0 FR1 FR2 K0 K1 K2 SI X Y Z DP PC PCH PCL SK SP CY RPS R1 R2 R3 R4L R4H Contents Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Clock control register MR (4 bits) Clock control register RG (1 bit) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W5 (4 bits) Timer control register W6 (4 bits) A/D control register Q1 (4 bits) A/D control register Q2 (4 bits) A/D control register Q3 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Port output format control register FR0 (4 bits) Port output format control register FR1 (4 bits) Port output format control register FR2 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) General-purpose register SI (8 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits 8) Stack pointer (3 bits) Carry flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 2 reload register (8 bits) Timer 3 reload register (8 bits) Timer 4 reload register (8 bits) Timer 4 reload register (8 bits)
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol PS T1 T2 T3 T4 T1F T2F T3F T4F WDF1 WEF INTE EXF0 EXF1 P ADF D P0 P1 P2 P3 P6 x y z p n i j A3A2A1A0
Contents Prescaler Timer 1 Timer 2 Timer 3 Timer 4 Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A/D conversion completion flag Port D (7 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (3 bits) Port P3 (2 bits) Port P6 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x
? () -- M(DP) a p, a C + x
Note : Some instructions of the 4583 Group has the skip function to unexecute the next described instruction. The 4583 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
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Notice: This is not a final specification. Some parametric limits are subject to change.
INDEX LIST OF INSTRUCTION FUNCTION
GroupMnemonic ing TAB TBA TAY TYA TEAB (A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) TABE (B) (E7-E4) (A) (E3-E0) TDA TAD (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 TAZ (A1, A0) (Z1, Z0) (A3, A2) 0 TAX TASP (A) (X) (A2-A0) (SP2-SP0) (A3) 0 LXY x, y (X) x x = 0 to 15 (Y) y y = 0 to 15 91, 122 111, 122 AM 109, 122 AMC (A) (A) + (M(DP)) (A) (A) + (M(DP)) + (CY) (CY) Carry An (A) (A) + n n = 0 to 15 AND OR DEY TAM j (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 XAM j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 XAMD j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
Note: p is 0 to 127 for M34583MD/ED.
Function
Page 102, 122
GroupMnemonic ing XAMI j
Function (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1
Page 121, 122
112, 122 111, 122 120, 122 112, 122
RAM to register transfer
TMA j
(M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
114, 122
Register to register transfer
LA n 104, 122 TABP p 112, 122 105, 122
(A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (DR2) 0 (DR1, DR0) (ROM(PC))9, 8 (B) (ROM(PC))7-4
90, 124
104, 124
112, 122
(A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 84, 124 84, 124
Arithmetic operation
RAM addresses
84, 124
LZ z INY
(Z) z z = 0 to 3 (Y) (Y) + 1
91, 122 90, 122 88, 122 107, 122
(A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0
85, 124 93, 124 96, 124 94, 124 100, 124 87, 124 93, 124
SC RC SZC CMA RAR
RAM to register transfer
120, 122
120, 122
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Notice: This is not a final specification. Some parametric limits are subject to change.
INDEX LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic ing SB j Function (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 SZB j (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Ba (PCL) a6-a0 (PCH) p (PCL) a6-a0 BLA p (PCH) p (PCL) (DR2-DR0, A3-A0) BM a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 TV2A TAI1 BML p, a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0 BMLA p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) TAW1 RTI (PC) (SK(SP)) (SP) (SP) - 1 95, 126 TW1A (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) 118, 128 110, 128 118, 128 110, 128 119, 128 (A) (W1) 109, 128 TPAA (PA0) (A0) 115, 128 86, 126 TAI2 TI2A (A) (I2) (I2) (A) 106, 128 113, 128 86, 126 TI1A (I1) (A) 113, 128 (V2) (A) (A) (I1) 118, 128 105, 128 86, 126 85, 126 85, 126 85, 126 100, 124 SNZ1 Page 95, 124 GroupMnemonic ing DI EI RB j 93, 124 SNZ0 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: NOP V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) 0 V11 = 1: NOP SEA n 97, 124 SNZI0 I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ? 98, 128 97, 128 97, 128 (INTE) 0 (INTE) 1 Function Page 88, 128 88, 128
Bit operation
Comparison operation
SEAM
97, 124
Interrupt operation
Branch operation
SNZI1
I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ?
98, 128
BL p, a
TAV1 TV1A TAV2
(A) (V1) (V1) (A) (A) (V2)
109, 128 118, 128 109, 128
Subroutine operation
RT
(PC) (SK(SP)) (SP) (SP) - 1
95, 126
Timer operation
TAW2 TW2A TAW3 TW3A
Return operation
RTS
(PC) (SK(SP)) (SP) (SP) - 1
95, 126
Note: p is 0 to 127 for M34583MD/ED.
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic TAW4 TW4A TAW5 TW5A TAW6 TW6A TABPS (A) (W4) (W4) (A) (A) (W5) (W5) (A) (A) (W6) (W6) (A) (B) (TPS7-TPS4) (A) (TPS3-TPS0) TPSAB (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) TAB1 (B) (T17-T14) (A) (T13-T10) 103, 130 SNZT4 101, 130 IAP0 OP0A TAB2 (B) (T27-T24) (A) (T23-T20) (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) IAP2 (T23-T20) (A) TAB3 (B) (T37-T34) (A) (T33-T30) T3AB (R37-R34) (B) (T37-T34) (B) (R33-R30) (A) (T33-T30) (A) TAB4 (B) (T47-T44) (A) (T43-T40) T4AB (R4L7-R4L4) (B) (T47-T44) (B) (R4L3-R4L0) (A) (T43-T40) (A) 102, 130 103, 130 101, 130 103, 130 103, 130 IAP1 101, 130 OP1A V21 = 0: (T4F) = 1 ? After skipping, (T4F) 0 V21 = 1: NOP (A) (P0) (P0) (A) (A) (P1) (P1) (A) (A2-A0) (P22-P20) (A3) 0 (P22-P20) (A2-A0) (A) (P3) (P3) (A) (A) (P6) (P6) (A) 99, 132 SNZT3 V20 = 0: (T3F) = 1 ? After skipping, (T3F) 0 V20 = 1: NOP 99, 132 115, 130 Function Page 110, 128 119, 128 TR1AB 110, 130 TR3AB 119, 130 T4R4L 111, 130 SNZT1 119, 130 104, 130 (T47-T44) (R4L7-R4L4) V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1: NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1: NOP 102, 130 99, 132 (R37-R34) (B) (R33-R30) (A) 117, 130 (R17-R14) (B) (R13-R10) (A) 117, 130 GroupMnemonic ing T4HAB Function (R4H7-R4H4) (B) (R4H3-R4H0) (A) Page 102, 130
Timer operation
SNZT2
99, 132
Timer operation
T1AB
(R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A)
89, 132 91, 132 89, 132 92, 132 89, 132 92, 132 90, 132 92, 132 90, 132 92, 132
T2AB
Input/Output operation
OP2A IAP3 OP3A IAP6 OP6A
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Notice: This is not a final specification. Some parametric limits are subject to change.
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic CLD RD (D) 1 (D(Y)) 0 (Y) = 0 to 6 SD (D(Y)) 1 (Y) = 0 to 6 (D(Y)) = 0 ? (Y) = 0 to 6 TADAB RCP SCP TAPU0 TPU0A (C) 0 (C) 1 (A) (PU0) (PU0) (A) (A) (PU1) (PU1) (A) (A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (FR0) (A) (FR1) (A) (FR2) (A) 94, 132 96, 132 107, 132 115, 132 108, 132 TAQ1 TPU1A TAK0 TK0A TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A 116, 132 TQ1A 106, 134 TAQ2 114, 134 TQ2A 106, 134 TAQ3 114, 134 TQ3A 106, 134 CMCK 114, 134 CRCK RC oscillator selected Quartz-crystal oscillator selected (RG0) (A0) (A) (MR) (MR) (A) 87, 134 87, 134 117, 134 107, 134 115, 134 112, 134 113, 134 113, 134 Ceramic resonator selected 87, 134 (Q3) (A) 116, 136 (A) (Q3) 108, 136 (Q2) (A) 116, 136 (A) (Q2) 108, 136 (Q1) (A) 116, 136 (A) (Q1) 108, 136 ADST (AD7-AD4) (B) (AD3-AD0) (A) (ADF) 0 A/D conversion starting SNZAD V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: NOP TAPU1 98, 136 84, 136 105, 136 96, 132 TALA SZD 101, 132 Function Page 86, 132 94, 132 GroupMnemonic ing TABAD Function In A/D conversion mode , (B) (AD9-AD6) (A) (AD5-AD2) In comparator mode, (B) (AD7-AD4) (A) (AD3-AD0) (A3, A2) (AD1, AD0) (A1, A0) 0 107, 136 Page 104, 136
Input/Output operation
Clock operation
A/D operation
CYCK TRGA TAMR TMRA
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Notice: This is not a final specification. Some parametric limits are subject to change.
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic NOP POF EPOF SNZP DWDT Function (PC) (PC) + 1 Transition to RAM back-up mode POF instruction valid (P) = 1 ? Stop of watchdog timer function enabled p6 0 when TABP p instruction is executed p6 1 when TABP p instruction is executed (WDF1) = 1 ? After skipping, (WDF1) 0 SVDE at RAM back-up: Voltage drop detection cicuit valid System reset occurrence (B) (SI7-SI4) (A) (SI3-SI0) (SI7-SI4) (B) (SI3-SI0) (A) 100, 136 Page 91, 136 93, 136 89, 136 98, 136 88, 136
Other operation
RBK
94, 136
SBK
96, 136
WRST
120, 136
SRST TABSI TSIAB
100, 136 105, 136 117, 136
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Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction code D9 0 0 0 1 1 0 n n n D0 n
2
0
6
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Overflow = 0
1
Operation:
(A) (A) + n n = 0 to 15
Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation.
ADST (A/D conversion STart)
Instruction code D9 1 0 1 0 0 1 1 1 1 D0 1
2
2
9
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(ADF) 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting (Q13 : bit 3 of A/D control register Q1)
Grouping: A/D conversion operation Description: Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
AM (Add accumulator and Memory)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 0
2
0
0
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) + (M(DP))
Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 1
2
0
0
B
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
(A) (A) + (M(DP)) + (CY) (CY) Carry
Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
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Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 0
2
0
1
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) AND (M(DP))
Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
B a (Branch to address a)
Instruction code D9 0 1 1 D0 a6 a5 a4 a3 a2 a1 a0
2
1
8 +a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PCL) a6 to a0
Grouping: Branch operation Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction code D9 0 1 Operation: 0 0 1 1 1 D0 p4 p3 p2 p1 p0
2
0 2
E +p p +a
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 a6 a5 a4 a3 a2 a1 a0 2
a 16
(PCH) p (PCL) a6 to a0
Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 127 for M34583MD/ED.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 0 0 1 0 0 0 0 D0 0
2
0 2
1 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 p4 0
p3 p2 p1 p0 2
p 16
(PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 127 for M34583MD/ED.
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Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BM a (Branch and Mark to address a in page 2)
Instruction code D9 0 1 0 D0 a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Instruction code D9 0 1 Operation: 0 0 1 1 0 D0 p4 p3 p2 p1 p0
2
0 2
C +p p +a
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 a6 a5 a4 a3 a2 a1 a0 2
a 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 127 for M34583MD/ED. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 0 1 1 0 0 0 0 D0 0
2
0 2
3 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 p4 0
p3 p2 p1 p0 2
p 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 127 for M34583MD/ED. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction code D9 0 0 0 0 0 1 0 0 0 D0 1
2
0
1
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D) 1
Grouping: Input/Output operation Description: Sets (1) to port D.
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CMA (CoMplement of Accumulator)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 02 0 1 C 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (A)
Grouping: Arithmetic operation Description: Stores the one's complement for register A's contents in register A.
CMCK (Clock select: ceraMic oscillation ClocK)
Instruction code D9 1 0 1 0 0 1 1 0 1 D0 0
2
2
9
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Ceramic oscillation circuit selected
Grouping: Clock control operation Description: Selects the ceramic oscillation circuit for main clock f(XIN).
CRCK (Clock select: Rc oscillation ClocK)
Instruction code D9 1 0 1 0 0 1 1 0 1 D0 1
2
2
9
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
RC oscillation circuit selected
Grouping: Clock control operation Description: Selects the RC oscillation circuit for main clock f(XIN).
CYCK (Clock select: crYstal oscillation ClocK)
Instruction code D9 1 0 1 0 0 1 1 1 0 D0 1
2
2
9
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Quartz-crystal oscillation circuit selected
Grouping: Clock control operation Description: Selects the quartz-crystal oscillation circuit for main clock f(XIN).
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DEY (DEcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 1 1 D0 1
2
0
1
7 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
Operation:
(Y) (Y) - 1
Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 0
2
0
0
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(INTE) 0
Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction code D9 1 0 1 0 0 1 1 1 0 D0 0
2
2
9
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Stop of watchdog timer function enabled
Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
EI (Enable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 1
2
0
0
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(INTE) 1
Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
EPOF (Enable POF instruction)
Instruction code D9 0 0 0 1 0 1 1 0 1 D0 1
2
0
5
B 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
POF instruction valid
Grouping: Other operation Description: Makes the immediate after POF instruction valid by executing the EPOF instruction.
IAP0 (Input Accumulator from port P0)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 0
2
2
6
0 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (P0)
Grouping: Input/Output operation Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 1
2
2
6
1 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (P1)
Grouping: Input/Output operation Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction code D9 1 0 0 1 1 0 0 0 1 D0 0
2
2
6
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (P22-P20) (A3) 0
Grouping: Input/Output operation Description: Transfers the input of port P2 to register A.
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP3 (Input Accumulator from port P3)
Instruction code D9 1 0 0 1 1 0 0 0 1 D0 1
2
2
6
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P3)
Grouping: Input/Output operation Description: Transfers the input of port P3 to register A.
IAP6 (Input Accumulator from port P6)
Instruction code D9 1 0 0 1 1 0 0 1 1 D0 0
2
2
6
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P6)
Grouping: Input/Output operation Description: Transfers the input of port P6 to register A.
INY (INcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 0 1 D0 1
2
0
1
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1
Operation:
(Y) (Y) + 1
Grouping: RAM addresses Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction code D9 0 0 0 1 1 1 n n n D0 n
2
0
7
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(A) n n = 0 to 15
Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LXY x, y (Load register X and Y with x and y)
Instruction code D9 1 1 D0 x3 x2 x1 x0 y3 y2 y1 y0
2
3
x
y
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(X) x x = 0 to 15 (Y) y y = 0 to 15
Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped.
LZ z (Load register Z with z)
Instruction code D9 0 0 0 1 0 0 1 0 D0 z1 z0
2
0
4
8 +z 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Z) z z = 0 to 3
Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z.
NOP (No OPeration)
Instruction code D9 0 0 0 0 0 0 0 0 0 D0 0
2
0
0
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PC) (PC) + 1
Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 0
2
2
2
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P0) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P0.
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP1A (Output port P1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 1
2
2
2
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P1) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P1.
OP2A (Output port P2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 1 D0 0
2
2
2
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P2) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P2.
OP3A (Output port P3 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 1 D0 1
2
2
2
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P3) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P3.
OP6A (Output port P6 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 1 1 D0 0
2
2
2
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P6) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P6.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OR (logical OR between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 12 0 1 9 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (A) OR (M(DP))
Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A.
POF (Power OFf)
Instruction code D9 0 0 0 0 0 0 0 0 1 D0 0
2
0
0
2 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
Transition to RAM back-up mode
Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction.
RAR (Rotate Accumulator Right)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 1
2
0
1
D
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
CY A3A2A1A0
Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
RB j (Reset Bit)
Instruction code D9 0 0 0 1 0 0 1 1 j D0 j
2
0
4
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 0 j = 0 to 3
Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RBK (Reset BanK flag)
Instruction code D9 0 0 0 1 0 0 0 0 0 D0 0
2
0
4
0 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
p6 0 when TABP p instruction is executed.
Grouping: Other operation Description: Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction.
RC (Reset Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 0
2
0
0
6
Number of words
16
Number of cycles 1
Flag CY 0
Skip condition -
1
Operation:
(CY) 0
Grouping: Arithmetic operation Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 0
2
2
8
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C) 0
Grouping: Input/Output operation Description: Clears (0) to port C.
RD (Reset port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 0
2
0
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D(Y)) 0 However, (Y) = 0 to 6
Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 0
2
0
4
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine.
RTI (ReTurn from Interrupt)
Instruction code D9 0 0 0 1 0 0 0 1 1 D0 02 0 4 6 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 1
2
0
4
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition Skip at uncondition
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction code D9 0 0 0 1 0 1 1 1 j D0 j
2
0
5
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 1 j = 0 to 3
Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SBK (Set BanK flag)
Instruction code D9 0 0 0 1 0 0 0 0 0 D0 1
2
0
4
1 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
p6 1 when TABP p instruction is executed.
Grouping: Other operation Description: Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction.
SC (Set Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 1
2
0
0
7
Number of words
16
Number of cycles 1
Flag CY 1
Skip condition -
1
Operation:
(CY) 1
Grouping: Arithmetic operation Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 1
2
2
8
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C) 1
Grouping: Input/Output operation Description: Sets (1) to port C.
SD (Set port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 1
2
0
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D(Y)) 1 (Y) = 0 to 6
Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction code D9 0 0 Operation: 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n D0 1
2
0 0
2 7
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (A) = n
2
n2
(A) = n ? n = 0 to 15
n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
SEAM (Skip Equal, Accumulator with Memory)
Instruction code D9 0 0 0 0 1 0 0 1 1 D0 0
2
0
2
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (A) = (M(DP))
1
Operation:
(A) = (M(DP)) ?
Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction code D9 0 0 0 0 1 1 1 0 0 D0 0
2
0
3
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V10 = 0: (EXF0) = 1
1
Operation:
V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1)
Grouping: Interrupt operation Description: When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is "1." After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction.
SNZ1 (Skip if Non Zero condition of external 1 interrupt request flag)
Instruction code D9 0 0 0 0 1 1 1 0 0 D0 1
2
0
3
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V11 = 0: (EXF1) = 1
1
Operation:
V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) 0 V11 = 1: SNZ1 = NOP (V11 : bit 1 of the interrupt control register V1)
Grouping: Interrupt operation Description: When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is "1." After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is "0," executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction code D9 1 0 1 0 0 0 0 1 1 D0 1
2
2
8
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V22 = 0: (ADF) = 1
1
Operation:
V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: SNZAD = NOP (V22 : bit 2 of the interrupt control register V2)
Grouping: A/D conversion operation Description: When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is "1." After skipping, clears (0) to the ADF flag. When the ADF flag is "0," executes the next instruction. When V22 = 1 : This instruction is equivalent to the NOP instruction.
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction code D9 0 0 0 0 1 1 1 0 1 D0 02 0 3 A 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition I12 = 0 : (INT0) = "L" I12 = 1 : (INT0) = "H"
Operation:
I12 = 0 : (INT0) = "L" ? I12 = 1 : (INT0) = "H" ? (I12 : bit 2 of the interrupt control register I1)
Grouping: Interrupt operation Description: When I12 = 0 : Skips the next instruction when the level of INT0 pin is "L." Executes the next instruction when the level of INT0 pin is "H." When I12 = 1 : Skips the next instruction when the level of INT0 pin is "H." Executes the next instruction when the level of INT0 pin is "L." Number of words 1 Number of cycles 1 Flag CY - Skip condition I22 = 0 : (INT1) = "L" I22 = 1 : (INT1) = "H"
SNZI1 (Skip if Non Zero condition of external 1 Interrupt input pin)
Instruction code D9 0 0 0 0 1 1 1 0 1 D0 12 0 3 B 16
Operation:
I22 = 0 : (INT1) = "L" ? I22 = 1 : (INT1) = "H" ? (I22 : bit 2 of the interrupt control register I2)
Grouping: Interrupt operation Description: When I22 = 0 : Skips the next instruction when the level of INT1 pin is "L." Executes the next instruction when the level of INT1 pin is "H." When I22 = 1 : Skips the next instruction when the level of INT1 pin is "H." Executes the next instruction when the level of INT1 pin is "L." Number of words
16
SNZP (Skip if Non Zero condition of Power down flag)
Instruction code D9 0 0 0 0 0 0 0 0 1 D0 1
2
0
0
3
Number of cycles 1
Flag CY -
Skip condition (P) = 1
1
Operation:
(P) = 1 ?
Grouping: Other operation Description: Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is "0."
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 0
2
2
8
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V12 = 0: (T1F) = 1
1
Operation:
V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1)
Grouping: Timer operation Description: When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is "1." After skipping, clears (0) to the T1F flag. When the T1F flag is "0," executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 1
2
2
8
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V13 = 0: (T2F) = 1
1
Operation:
V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1)
Grouping: Timer operation Description: When V13 = 0 : Skips the next instruction when timer 2 interrupt request flag T2F is "1." After skipping, clears (0) to the T2F flag. When the T2F flag is "0," executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction.
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 1 D0 0
2
2
8
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V20 = 0: (T3F) = 1
1
Operation:
V20 = 0: (T3F) = 1 ? After skipping, (T3F) 0 V20 = 1: SNZT3 = NOP (V20 = bit 0 of interrupt control register V2)
Grouping: Timer operation Description: When V20 = 0 : Skips the next instruction when timer 3 interrupt request flag T3F is "1." After skipping, clears (0) to the T3F flag. When the T3F flag is "0," executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction.
SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 1 D0 1
2
2
8
3 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition V21 = 0: (T4F) = 1
Operation:
V21 = 0: (T4F) = 1 ? After skipping, (T4F) 0 V21 = 1: SNZT4 = NOP (V21 = bit 1 of interrupt control register V2)
Grouping: Timer operation Description: When V21 = 0 : Skips the next instruction when timer 4 interrupt request flag T4F is "1." After skipping, clears (0) to the T4F flag. When the T4F flag is "0," executes the next instruction. When V21 = 1 : This instruction is equivalent to the NOP instruction.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SRST (System ReSeT)
Instruction code D9 0 0 0 0 0 0 0 0 0 D0 1
2
0
0
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
System reset occurrence
Grouping: Other operation Description: System reset occurs.
SVDE (Set Voltage Detector Enable flag)
Instruction code D9 1 0 1 0 0 1 0 0 1 D0 1
2
2
9
3 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
At RAM back-up: Voltage drop detection circuit is valid.
Grouping: Other operation Description: Validates the voltage drop detection circuit at RAM back-up mode when VDCE pin is "H".
SZB j (Skip if Zero, Bit)
Instruction code D9 0 0 0 0 1 0 0 0 j D0 j
2
0
2
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Mj(DP)) = 0 j = 0 to 3
1
Operation:
(Mj(DP)) = 0 ? j = 0 to 3
Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1."
SZC (Skip if Zero, Carry flag)
Instruction code D9 0 0 0 0 1 0 1 1 1 D0 1
2
0
2
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (CY) = 0
1
Operation:
(CY) = 0 ?
Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is "0." After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is "1."
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZD (Skip if Zero, port D specified by register Y)
Instruction code D9 0 0 Operation: 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0
2
0 0
2 2
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (D(Y)) = 0
(Y) = 0 to 6
2
12
B 16
(D(Y)) = 0 ? (Y) = 0 to 6
Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when the bit is "1."
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 D0 0
2
2
3
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(T17-T14) (B) (R17-R14) (B) (T13-T10) (A) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 D0 1
2
2
3
1
16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(T27-T24) (B) (R27-R24) (B) (T23-T20) (A) (R23-R20) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 1 D0 0
2
2
3
2 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(T37-T34) (B) (R37-R34) (B) (T33-T30) (A) (R33-R30) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3. Transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T4AB (Transfer data to timer 4 and register R4L from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 1 D0 12 2 3 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(T47-T44) (B) (R4L7-R4L4) (B) (T43-T40) (A) (R4L3-R4L0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L.
T4HAB (Transfer data to register R4H from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 1 1 D0 12 2 3 7 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(R4H7-R4H4) (B) (R4H3-R4H0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4H. Transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4H.
T4R4L (Transfer data to timer 4 from register R4L)
Instruction code D9 1 0 1 0 0 1 0 1 1 D0 1
2
2
9
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(T47-T44) (R4L7-R4L4) (T43-T40) (R4L3-R4L0)
Grouping: Timer operation Description: Transfers the contents of reload register R4L to timer 4.
TAB (Transfer data to Accumulator from register B)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 0
2
0
1
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (B)
Grouping: Register to register transfer Description: Transfers the contents of register B to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 0
2
2
7
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T17-T14) (A) (T13-T10)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T17-T14) of timer 1 to register B. Transfers the low-order 4 bits (T13-T10) of timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 1
2
2
7
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T27-T24) (A) (T23-T20)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T27-T24) of timer 2 to register B. Transfers the low-order 4 bits (T23-T20) of timer 2 to register A.
TAB3 (Transfer data to Accumulator and register B from timer 3)
Instruction code D9 1 0 0 1 1 1 0 0 1 D0 0
2
2
7
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T37-T34) (A) (T33-T30)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T37-T34) of timer 3 to register B. Transfers the low-order 4 bits (T33-T30) of timer 3 to register A.
TAB4 (Transfer data to Accumulator and register B from timer 4)
Instruction code D9 1 0 0 1 1 1 0 0 1 D0 1
2
2
7
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T47-T44) (A) (T43-T40)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T47-T44) of timer 4 to register B. Transfers the low-order 4 bits (T43-T40) of timer 4 to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction code D9 1 0 0 1 1 1 1 0 0 D0 1
2
2
7
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
In A/D conversion mode (Q13 = 0), (B) (AD9-AD6) (A) (AD5-AD2) In comparator mode (Q13 = 1), (B) (AD7-AD4) (A) (AD3-AD0) (Q13 : bit 3 of A/D control register Q1)
Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9-AD6) of register AD to register B, and the middle-order 4 bits (AD5-AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7-AD4) of register AD to register B, and the low-order 4 bits (AD3-AD0) of register AD to register A. D0 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
TABE (Transfer data to Accumulator and register B from register E)
Instruction code D9 0 0 0 0 1 0 1 0 1 02 0 2 A 16
Operation:
(B) (E7-E4) (A) (E3-E0)
Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction code D9 0 0 1 0 D0 p5 p4 p3 p2 p1 p0
2
0
8 +p
p
Number of words
16
Number of cycles 3
Flag CY -
Skip condition -
1
Operation:
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (DR2) 0 (DR1, DR0) (ROM(PC))9, 8 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 D9 1 0 0 1 1 1 0
Arithmetic operation N o t e : p i s 0 t o 1 2 7 f o r Grouping: M34583MD/ED. Description: Transfers bits 9 and 8 to register D, bits 7 to 4 When this instruction to register B and bits 3 to 0 to register A. is executed, be careful These bits 7 to 0 are the ROM pattern in adnot to over the stack dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified because 1 stage of by registers A and D in page p. stack register is used. The pages which can be referred as follows; after the SBK instruction: 64 to 127 after the RBK instruction: 0 to 63 after system is released from reset or returned from RAM back-up: 0 to 63. D0 1 0 1
2
TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction code 2 7 5 Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (TPS7-TPS4) (A) (TPS3-TPS0)
Grouping: Timer operation Description: Transfers the high-order 4 bits (TPS7- TPS4) of prescaler to register B, and transfers the low-order 4 bits (TPS3-TPS0) of prescaler to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABSI (Transfer data to Accumulator and register B from register SI)
Instruction code D9 1 0 0 1 1 1 1 0 0 D0 02 2 7 8 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(B) (SI7-SI4) (A) (SI3-SI0)
Grouping: Other operation Description: Transfers the high-order 4 bits (SI7-SI4) of register SI to register B, and transfers the low-order 4 bits (SI3-SI0) of register SI to register A.
TAD (Transfer data to Accumulator from register D)
Instruction code D9 0 0 0 1 0 1 0 0 0 D0 1
2
0
5
1 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A2-A0) (DR2-DR0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Note: When this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
TADAB (Transfer data to register AD from Accumulator from register B)
Instruction code D9 1 0 0 0 1 1 1 0 0 D0 1
2
2
3
9 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(AD7-AD4) (B) (AD3-AD0) (A)
Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7-AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3-AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) D0 Number of words
16
TAI1 (Transfer data to Accumulator from register I1)
Instruction code D9 1 0 0 1 0 1 0 0 1 1
2
2
5
3
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (I1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAI2 (Transfer data to Accumulator from register I2)
Instruction code D9 1 0 0 1 0 1 0 1 0 D0 0
2
2
5
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (I2)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I2 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction code D9 1 0 0 1 0 1 0 1 1 D0 0
2
2
5
6 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (K0)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruction code D9 1 0 0 1 0 1 1 0 0 D0 1
2
2
5
9 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (K1)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction code D9 1 0 0 1 0 1 1 0 1 D0 0
2
2
5
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K2)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TALA (Transfer data to Accumulator from register LA)
Instruction code D9 1 0 0 1 0 0 1 0 0 D0 1
2
2
4
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A3, A2) (AD1, AD0) (A1, A0) 0
Grouping: A/D conversion operation Description: Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. Note: After this instruction is executed, "0" is stored to the low-order 2 bits (A1, A0) of register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction code D9 1 0 1 1 0 0 j j j D0 j
2
2
C
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
TAMR (Transfer data to Accumulator from register MR)
Instruction code D9 1 0 0 1 0 1 0 0 1 D0 0
2
2
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (MR)
Grouping: Clock operation Description: Transfers the contents of clock control register MR to register A.
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction code D9 1 0 0 1 0 1 0 1 1 D0 1
2
2
5
7 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (PU0)
Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction code D9 1 0 0 1 0 1 1 1 1 D0 0
2
2
5
E 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (PU1)
Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A.
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction code D9 1 0 0 1 0 0 0 1 0 D0 0
2
2
4
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (Q1)
Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q1 to register A.
TAQ2 (Transfer data to Accumulator from register Q2)
Instruction code D9 1 0 0 1 0 0 0 1 0 D0 1
2
2
4
5 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (Q2)
Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q2 to register A.
TAQ3 (Transfer data to Accumulator from register Q3)
Instruction code D9 1 0 0 1 0 0 0 1 1 D0 0
2
2
4
6 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (Q3)
Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q3 to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction code D9 0 0 0 1 0 1 0 0 0 D0 0
2
0
5
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (SP2-SP0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Note: After this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 0
2
0
5
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 1
2
0
5
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V2)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A.
TAW1 (Transfer data to Accumulator from register W1)
Instruction code D9 1 0 0 1 0 0 1 0 1 D0 1
2
2
4
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W1)
Grouping: Timer operation Description: Transfers the contents of timer control register W1 to register A.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW2 (Transfer data to Accumulator from register W2)
Instruction code D9 1 0 0 1 0 0 1 1 0 D0 0
2
2
4
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W2)
Grouping: Timer operation Description: Transfers the contents of timer control register W2 to register A.
TAW3 (Transfer data to Accumulator from register W3)
Instruction code D9 1 0 0 1 0 0 1 1 0 D0 1
2
2
4
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W3)
Grouping: Timer operation Description: Transfers the contents of timer control register W3 to register A.
TAW4 (Transfer data to Accumulator from register W4)
Instruction code D9 1 0 0 1 0 0 1 1 1 D0 0
2
2
4
E 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (W4)
Grouping: Timer operation Description: Transfers the contents of timer control register W4 to register A.
TAW5 (Transfer data to Accumulator from register W5)
Instruction code D9 1 0 0 1 0 0 1 1 1 D0 1
2
2
4
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W5)
Grouping: Timer operation Description: Transfers the contents of timer control register W5 to register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW6 (Transfer data to Accumulator from register W6)
Instruction code D9 1 0 0 1 0 1 0 0 0 D0 0
2
2
5
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W6)
Grouping: Timer operation Description: Transfers the contents of timer control register W6 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 0
2
0
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (X)
Grouping: Register to register transfer Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 1
2
0
1
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (Y)
Grouping: Register to register transfer Description: Transfers the contents of register Y to register A.
TAZ (Transfer data to Accumulator from register Z)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 1
2
0
5
3 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A1, A0) (Z1, Z0) (A3, A2) 0
Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, "0" is stored to the high-order 2 bits (A3, A2) of register A.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TBA (Transfer data to register B from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 1 D0 0
2
0
0
E 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(B) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction code D9 0 0 0 0 1 0 1 0 0 D0 1
2
0
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(DR2-DR0) (A2-A0)
Grouping: Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction code D9 0 0 0 0 0 1 1 0 1 D0 0
2
0
1
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(E7-E4) (B) (E3-E0) (A)
Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E7-E4) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E.
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 0 D0 0
2
2
2
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR0.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 0 D0 1
2
2
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 1 D0 0
2
2
2
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR2.
TI1A (Transfer data to register I1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 12 2 1 7 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(I1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I1.
TI2A (Transfer data to register I2 from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 0 0 D0 0
2
2
1
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(I2) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I2.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK0A (Transfer data to register K0 from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 0 1 D0 1
2
2
1
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 0
2
2
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K1.
TK2A (Transfer data to register K2 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 1
2
2
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K2.
TMA j (Transfer data to Memory from Accumulator)
Instruction code D9 1 0 1 0 1 1 j j j D0 j
2
2
B
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TMRA (Transfer data to register MR from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 0
2
2
1
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(MR) (A)
Grouping: Other operation Description: Transfers the contents of register A to clock control register MR.
TPAA (Transfer data to register PA from Accumulator)
Instruction code D9 1 0 1 0 1 0 1 0 1 D0 0
2
2
A
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PA0) (A0)
Grouping: Timer operation Description: Transfers the contents of lowermost bit (A0) register A to timer control register PA.
TPSAB (Transfer data to Pre-Scaler from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 1 0 D0 1
2
2
3
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 0 D0 1
2
2
2
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU0.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 115 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 1 D0 0
2
2
2
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU1.
TQ1A (Transfer data to register Q1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 1 0 D0 0
2
2
0
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Q1) (A)
Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q1.
TQ2A (Transfer data to register Q2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 1 0 D0 1
2
2
0
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Q2) (A)
Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q2.
TQ3A (Transfer data to register Q3 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 1 1 D0 0
2
2
0
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Q3) (A)
Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q3.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 1 1 D0 1
2
2
3
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(R17-R14) (B) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R17-R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13-R10) of reload register R1.
TR3AB (Transfer data to register R3 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 0 1 D0 1
2
2
3
B 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(R37-R34) (B) (R33-R30) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R37-R34) of reload register R3, and the contents of register A to the low-order 4 bits (R33-R30) of reload register R3.
TRGA (Transfer data to register RG from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 0 0 D0 1
2
2
0
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(RG0) (A0)
Grouping: Clock control operation Description: Transfers the contents of register A to register RG.
TSIAB (Transfer data to register SI from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 0 0 D0 0
2
2
3
8 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(SI7-SI4) (B) (SI3-SI0) (A)
Grouping: Other operation Description: Transfers the contents of register B to the high-order 4 bits (SI7-SI4) of register SI, and transfers the contents of register A to the low-order 4 bits (SI3-SI0) of register SI.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV1A (Transfer data to register V1 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 1
2
0
3
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(V1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 02 0 3 E 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(V2) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 0
2
2
0
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W1) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 1
2
2
0
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W2) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW3A (Transfer data to register W3 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 0 D0 02 2 1 0 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(W3) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W3.
TW4A (Transfer data to register W4 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 0 D0 12 2 1 1 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(W4) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W4.
TW5A (Transfer data to register W5 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 1 D0 0
2
2
1
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W5) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W5.
TW6A (Transfer data to register W6 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 1 D0 12 2 1 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(W6) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W6.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TYA (Transfer data to register Y from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 0 D0 0
2
0
0
C 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Y) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register Y.
WRST (Watchdog timer ReSeT)
Instruction code D9 1 0 1 0 1 0 0 0 0 D0 0
2
2
A
0 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition (WDF1) = 1
Operation:
(WDF1) = 1 ? After skipping, (WDF1) 0
Grouping: Other operation Description: Skips the next instruction when watchdog timer flag WDF1 is "1." After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is "0," executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction.
XAM j (eXchange Accumulator and Memory data)
Instruction code D9 1 0 1 1 0 1 j j j D0 j
2
2
D
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction code D9 1 0 1 1 1 1 j j j D0 j
2
2
F
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 120 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction code D9 1 0 1 1 1 0 j j j D0 j
2
2
E
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 121 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0
01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x x = 0 to 15 (Y) y y = 0 to 15 (Z) z z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1
Register to register transfer
TEAB TABE TDA TAD TAZ TAX TASP LXY x, y
x3 x2 x1 x0 y3 y2 y1 y0
RAM addresses
LZ z INY DEY
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 1 1
1 0 0
0 0 1
z1 z0 1 1 1 1
048 +z 013 017
1 1 1
1 1 1
TAM j
1
0
1
1
0
0
j
j
j
j
2Cj
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2Dj
1
1
RAM to register transfer
XAMD j
1
0
1
1
1
1
j
j
j
j
2Fj
1
1
XAMI j
1
0
1
1
1
0
j
j
j
j
2Ej
1
1
TMA j
1
0
1
0
1
1
j
j
j
j
2Bj
1
1
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 122 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - Continuous description - (Y) = 0 (Y) = 15
- - - - - - - - - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E7-E4) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E. Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits (E3-E0) of register E to register A. Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
- - -
-
-
-
-
(Y) = 15
-
(Y) = 0
-
-
-
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 123 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n
07n
1
1
(A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) (DR2) 0 (DR1, DR0) (ROM(PC))9, 8 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (SK(SP)) (PC) (SP) (SP) - 1 (A) (A) + (M(DP)) (A) (A) + (M(DP)) +(CY) (CY) Carry (A) (A) + n n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
08p +p
1
3
AM
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 0
1 1 n
0 0 n
1 1 n
0 1 n
00A 00B 06n
1 1 1
1 1 1
Arithmetic operation
AMC An
AND OR SC RC SZC CMA RAR SB j
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0
0 0 0 0 1 0 0 0 0 1
1 1 0 0 0 1 1 1 0 0
1 1 0 0 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 0 0 j j j
0 1 1 0 1 0 1 j j j
018 019 007 006 02F 01C 01D 05C +j 04C +j 02j
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
(A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ?
Bit operation
RB j SZB j
SEAM
0
0
0
0
1
0
0
1
1
0
026
1
1
Comparison operation
SEA n
0 0
0 0
0 0
0 1
1 1
0 1
0 n
1 n
0 n
1 n
025 07n
2
2
(A) = n ? n = 0 to 15
Note: p is 0 to 127 for M34583MD/ED.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 124 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
Continuous description -
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 9 and 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. The pages which can be referred as follows; after the SBK instruction: 64 to 127 after the RBK instruction: 0 to 63 after system is released from reset or returned from RAM back-up: 0 to 63.
-
- - Overflow = 0
-
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. - Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0." Stores the one's complement for register A's contents in register A.
- - - - (CY) = 0 - - - - (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP))
- - 1 0 - -
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - - - Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1." Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
-
(A) = n
-
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 125 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 0 0 0 1 1 1 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0
18a +a 0Ep +p 2pa +a 010 2pp 1aa
1 2
1 2
(PCL) a6-a0 (PCH) p (Note) (PCL) a6-a0
Branch operation
p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 0 0 0 0 0
2
2
(PCH) p (Note) (PCL) (DR2-DR0, A3-A0)
p5 p4 0 0
p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
1
1
Subroutine operation
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0,A3-A0) (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1
BML p, a
0 1
0 0 0 0
1
1
0
p4 p3 p2 p1 p0
0Cp +p 2pa +a 030 2pp
2
2
p5 a6 a5 a4 a3 a2 a1 a0 0 0 1 1 0 0 0 0 0
BMLA p
0 1
2
2
p5 p4 0
p3 p2 p1 p0
RTI
0
0
0
1
0
0
0
1
1
0
046
1
1
Return operation
RT
0
0
0
1
0
0
0
1
0
0
044
1
2
RTS
0
0
0
1
0
0
0
1
0
1
045
1
2
Note: p is 0 to 127 for M34583MD/ED.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 126 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
- -
- -
Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p.
-
-
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine.
-
-
Skip at uncondition
-
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 127 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DI EI SNZ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0
004 005 038
1 1 1
1 1 1
(INTE) 0 (INTE) 1 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: SNZ0 = NOP V11 = 0: (EXF1) = 1 ? After skipping, (EXF1) 0 V11 = 1: SNZ1 = NOP I12 = 1 : (INT0) = "H" ? I12 = 0 : (INT0) = "L" ?
SNZ1
0
0
0
0
1
1
1
0
0
1
039
1
1
SNZI0
0
0
0
0
1
1
1
0
1
0
03A
1
1
Interrupt operation
SNZI1
0
0
0
0
1
1
1
0
1
1
03B
1
1
I22 = 1 : (INT1) = "H" ? I22 = 0 : (INT1) = "L" ?
TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TPAA TAW1 TW1A TAW2
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0
0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1
0 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 0
1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 1 0
0 1 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0
0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 0 1
054 03F 055 03E 253 217 254 218 2AA 24B 20E 24C 20F 24D 210 24E 211
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (I2) (I2) (A) (PA0) (A0) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) (A) (W4) (W4) (A)
Timer operation
TW2A TAW3 TW3A TAW4 TW4A
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 128 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
- - V10 = 0: (EXF0) = 1
- - -
Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is "1." After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When V11 = 0 : Skips the next instruction when external 1 interrupt request flag EXF1 is "1." After skipping, clears (0) to the EXF1 flag. When the EXF1 flag is "0," executes the next instruction. When V11 = 1 : This instruction is equivalent to the NOP instruction. (V11: bit 1 of interrupt control register V1) When I12 = 1 : Skips the next instruction when the level of INT0 pin is "H." (I12: bit 2 of interrupt control register I1) When I12 = 0 : Skips the next instruction when the level of INT0 pin is "L."
V11 = 0: (EXF1) = 1
-
(INT0) = "H" However, I12 = 1 (INT0) = "L" However, I12 = 0 (INT1) = "H" However, I22 = 1 (INT1) = "L" However, I22 = 0 - - - - - - - - - - - - - - - - -
- -
- - - - - - - - - - - - - - - - - - -
When I22 = 1 : Skips the next instruction when the level of INT1 pin is "H." (I22: bit 2 of interrupt control register I2) When I22 = 0 : Skips the next instruction when the level of INT1 pin is "L." Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 129 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAW5 TW5A TAW6 TW6A TABPS TPSAB 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1
24F 212 250 213 275 235
1 1 1 1 1 1
1 1 1 1 1 1
(A) (W5) (W5) (A) (A) (W6) (W6) (A) (B) (TPS7-TPS4) (A) (TPS3-TPS0) (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) (B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (B) (T27-T24) (A) (T23-T20) (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A) (B) (T37-T34) (A) (T33-T30) (R37-R34) (B) (T37-T34) (B) (R33-R30) (A) (T33-T30) (A) (B) (T47-T44) (A) (T43-T40) (R4L7-R4L4) (B) (T47-T44) (B) (R4L3-R4L0) (A) (T43-T40) (A) (R4H7-R4H4) (B) (R4H3-R4H0) (A) (R17-R14) (B) (R13-R10) (A) (R37-R34) (B) (R33-R30) (A) (T47-T40) (R4L7-R4L0)
TAB1 T1AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
0 0
270 230
1 1
1 1
TAB2 T2AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
1 1
271 231
1 1
1 1
Timer operation
TAB3 T3AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
0 0
272 232
1 1
1 1
TAB4 T4AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
1 1
1 1
273 233
1 1
1 1
T4HAB TR1AB TR3AB T4R4L
1 1 1 1
0 0 0 0
0 0 0 1
0 0 0 0
1 1 1 0
1 1 1 1
0 1 1 0
1 1 0 1
1 1 1 1
1 1 1 1
237 23F 23B 297
1 1 1 1
1 1 1 1
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 130 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
- - - - - -
- - - - - -
Transfers the contents of timer control register W5 to register A. Transfers the contents of register A to timer control register W5. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
- -
- -
- -
- -
Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2, and transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
- -
- -
Transfers the high-order 4 bits of timer 3 to register B, and transfers the low-order 4 bits of timer 3 to register A. Transfers the contents of register B to the high-order 4 bits of timer 3 and timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 and timer 3 reload register R3.
- -
- -
Transfers the high-order 4 bits of timer 4 to register B, and transfers the low-order 4 bits of timer 4 to register A. Transfers the contents of register B to the high-order 4 bits of timer 4 and timer 4 reload register R4L, and transfers the contents of register A to the low-order 4 bits of timer 4 and timer 4 reload register R4L.
- - - -
- - - -
Transfers the contents of register B to the high-order 4 bits of timer 4 reload register R4H, and transfers the contents of register A to the low-order 4 bits of timer 4 reload register R4H. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1. Transfers the contents of register B to the high-order 4 bits of timer 3 reload register R3, and transfers the contents of register A to the low-order 4 bits of timer 3 reload register R3. Transfers the contents of timer 4 reload register R4L to timer 4.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 131 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SNZT1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 RCP SCP TAPU0 TPU0A TAPU1 TPU1A 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0
280 281 282 283 260 220 261 221 262 222 263 223 266 226 011 014 015 024 02B 28C 28D 257 22D 25E 22E
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 0: NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 0: NOP V20 = 0: (T3F) = 1 ? After skipping, (T3F) 0 V20 = 0: NOP V21 = 0: (T4F) = 1 ? After skipping, (T4F) 0 V21 = 0: NOP (A) (P0) (P0) (A) (A) (P1) (P1) (A) (A2-A0) (P22-P20) (A3) 0 (P22-P20) (A2-A0) (A) (P3) (P3) (A) (A) (P6) (P6) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 6 (D(Y)) 1 (Y) = 0 to 6 (D(Y)) = 0 ? (Y) = 0 to 6 C0 C1 (A) (PU0) (PU0) (A) (A) (PU1) (PU1) (A)
Timer operation Input/Output operation
SNZT2 SNZT3 SNZT4 IAP0 OP0A IAP1 OP1A IAP2 OP2A IAP3 OP3A IAP6 OP6A CLD RD SD SZD
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 132 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
V12 = 0: (T1F) = 1 V13 = 0: (T2F) =1 V20 = 0: (T3F) = 1 V21 = 0: (T4F) =1 - - - - - - - - - - - - - (D(Y)) = 0 However, (Y)=0 to 6 - - - - - -
- - - - - - - - - - - - - - - - - -
Skips the next instruction when the contents of bit 2 (V12) of interrupt control register V1 is "0" and the contents of T1F flag is "1." After skipping, clears (0) to T1F flag. Skips the next instruction when the contents of bit 3 (V13) of interrupt control register V1 is "0" and the contents of T2F flag is "1." After skipping, clears (0) to T2F flag. Skips the next instruction when the contents of bit 0 (V20) of interrupt control register V2 is "0" and the contents of T3F flag is "1." After skipping, clears (0) to T3F flag. Skips the next instruction when the contents of bit 1 (V21) of interrupt control register V2 is "0" and the contents of T4F flag is "1." After skipping, clears (0) to T4F flag. Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Outputs the contents of register A to port P2. Transfers the input of port P3 to register A. Outputs the contents of register A to port P3. Transfers the input of port P6 to register A. Outputs the contents of register A to port P6. Sets (1) to all port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when a bit of port D specified by register Y is "1." Clears (0) to port C. Sets (1) to port C. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1.
- - - - - -
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 133 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAK0 TK0A TAK1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1
256 21B 259 214 25A 215 228 229 22A 29A 29B 29D 209 252 216 279
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (FR0) (A) (FR1) (A) (FR2) (A) Ceramic resonator selected RC oscillator selected Quartz-crystal oscillator selected (RG0) (A0) (A) (MR) (MR) (A) Q13 = 0: (B) (AD9-AD6) (A) (AD5-AD2) Q13 = 1: (B) (AD7-AD4) (A) (AD3-AD0) (A3, A2) (AD1, AD0) (A1, A0) 0 (AD7-AD4) (B) (AD3-AD0) (A) (ADF) 0 A/D conversion starting V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: NOP (A) (Q1) (Q1) (A) (A) (Q2) (Q2) (A) (A) (Q3) (Q3) (A)
Input/Output operation Clock operation
TK1A TAK2 TK2A TFR0A TFR1A TFR2A CMCK CRCK CYCK TRGA TAMR TMRA TABAD
TALA TADAB
1 1
0 0
0 0
1 0
0 1
0 1
1 1
0 0
0 0
1 1
249 239
1 1
1 1
A/D conversion operation
ADST
1
0
1
0
0
1
1
1
1
1
29F
1
1
SNZAD
1
0
1
0
0
0
0
1
1
1
287
1
1
TAQ1 TQ1A TAQ2 TQ2A TAQ3 TQ3A
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
1 0 1 0 1 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
1 1 1 1 1 1
0 0 0 0 1 1
0 0 1 1 0 0
244 204 245 205 246 206
1 1 1 1 1 1
1 1 1 1 1 1
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 134 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - -
Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0 . Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transferts the contents of register A to port output format control register FR0. Transferts the contents of register A to port output format control register FR1. Transferts the contents of register A to port output format control register FR2. Selects the ceramic resonator for main clock f(XIN). Selects the RC oscillation circuit for main clock f(XIN). Selects the quartz-crystal oscillation circuit for main clock f(XIN). Transfers the contents of clock control regiser RG to register A. Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR. In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9-AD6) of register AD to register B, and the middle-order 4 bits (AD5-AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7-AD4) of register AD to register B, and the low-order 4 bits (AD3-AD0) of register AD to register A. (Q13: bit 3 of A/D control register Q1) Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7-AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3-AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. (Q13 = bit 3 of A/D control register Q1) When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is "1." After skipping, clears (0) to the ADF flag. When the ADF flag is "0," executes the next instruction. (V22: bit 2 of interrupt control register V2) Transfers the contents of A/D control register Q1 to register A. Transfers the contents of register A to A/D control register Q1. Transfers the contents of A/D control register Q2 to register A. Transfers the contents of register A to A/D control register Q2. Transfers the contents of A/D control register Q3 to register A. Transfers the contents of register A to A/D control register Q3.
- -
- -
-
-
V22 = 0: (ADF) = 1
-
- - - - - -
- - - - - -
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 135 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOP POF EPOF SNZP WRST 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0
000 002 05B 003 2A0
1 1 1 1 1
1 1 1 1 1
(PC) (PC) + 1 Transition to RAM back-up mode POF instruction valid (P) = 1 ? (WDF1) = 1 ? After skipping, (WDF1) 0 Stop of watchdog timer function enabled System reset occurrence At RAM back-up: voltage drop detection circuit valid. p6 0 when TABP p instruction is executed p6 1 when TABP p instruction is executed (B) (SI7-SI4) (A) (SI3-SI0) (SI7-SI4) (B) (SI3-SI0) (A)
Other operation
DWDT SRST SVDE RBK SBK TABSI TSIAB
1 0 1 0 0 1 1
0 0 0 0 0 0 0
1 0 1 0 0 0 0
0 0 0 1 1 1 0
0 0 0 0 0 1 1
1 0 1 0 0 1 1
1 0 0 0 0 1 1
1 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 1 0 1 0 0
29C 001 293 040 041 278 238
1 1 1 1 1 1 1
1 1 1 1 1 1 1
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 136 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
Skip condition
Carry flag CY
Datailed description
- - - (P) = 1 (WDF1) = 1
- - - - -
No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Makes the immediate after POF instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Skips the next instruction when watchdog timer flag WDF1 is "1." After skipping, clears (0) to the WDF1 flag. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. System reset occurs. The voltage drop detection circuit is valid at RAM back-up mode when VDCE pin is "H". Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid only for the TABP p instruction. Transfers the high-order 4 bits (SI7-SI4) of register SI to register B, and transfers the low-order 4 bits (SI3- SI0) of register SI to register A. Transfers the contents of register B to the high-order 4 bits (SI7-SI4) of register SI, and transfers the contents of register A to the low-order 4 bits (SI3-SI0) of register SI.
- - - - - - -
- - - - - - -
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 137 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
INSTRUCTION CODE TABLE
D9-D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP
01 BLA
02
03
04
05
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML
0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA RBK TASP 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - - - - - - - - SNZ0 SBK - - RT TAD TAX TAZ TAV1
TABP TABP TABP TABP BML 48 32 0 16 TABP TABP TABP TABP BML 49 33 1 17 TABP TABP TABP TABP BML 50 34 2 18 TABP TABP TABP TABP BML 51 35 3 19 TABP TABP TABP TABP BML 36 52 4 20 TABP TABP TABP TABP BML 53 37 5 21 TABP TABP TABP TABP BML 38 54 6 22 TABP TABP TABP TABP BML 55 39 7 23 TABP TABP TABP TABP BML 40 56 8 24 TABP TABP TABP TABP BML 57 41 9 25 TABP TABP TABP TABP BML 42 58 10 26 TABP TABP TABP TABP BML 59 43 11 27 TABP TABP TABP TABP BML 60 44 12 28 TABP TABP TABP TABP BML 61 45 13 29 TABP TABP TABP TABP BML 62 46 14 30 TABP TABP TABP TABP BML 47 63 15 31
SRST CLD POF -
SNZP INY DI EI RC SC - - AM AMC TYA - TBA - RD SD - DEY AND OR
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
TDA SNZ1
TEAB TABE SNZI0 - CMA RAR TAB TAY - - - - SNZI1 - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 * A page referred by the TABP instruction can be switched by the SBK and RBK instructions. * The pages which can be referred by the TABP instruction after the SBK instruction is executed are 64 to 127. (Ex. TABP 0 TABP 64) * The pages which can be referred by the TABP instruction after the RBK instruction is executed are 0 to 63. * When the SBK instruction is not used, the pages which can be referred by the TABP instruction are 0 to 63.
BL BML BLA BMLA SEA SZD
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
INSTRUCTION CODE TABLE (continued)
D9-D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111
20 - - - -
21
22
23
24 - - - -
25
26
27
28
29 - - -
2A WRST - - - - - - - - -
2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15
2C TAM 0 TAM 1 TAM 2 TAM 3 TAM 4 TAM 5 TAM 6 TAM 7 TAM 8 TAM 9 TAM 10 TAM 11 TAM 12 TAM 13 TAM 14 TAM 15
2D
2E
2F
30-3F
TW3A OP0A T1AB TW4A OP1A T2AB TW5A OP2A T3AB TW6A OP3A T4AB - - -
TAW6 IAP0 TAB1 SNZT1 - IAP1 TAB2 SNZT2
XAM XAMI XAMD LXY 0 0 0 XAM XAMI XAMD LXY 1 1 1 XAM XAMI XAMD LXY 2 2 2 XAM XAMI XAMD LXY 3 3 3 XAM XAMI XAMD LXY 4 4 4 XAM XAMI XAMD LXY 5 5 5 XAM XAMI XAMD LXY 6 6 6 XAM XAMI XAMD LXY 7 7 7 XAM XAMI XAMD LXY 8 8 8 XAM XAMI XAMD LXY 9 9 9 XAM XAMI XAMD LXY 10 10 10 XAM XAMI XAMD LXY 11 11 11 XAM XAMI XAMD LXY 12 12 12 XAM XAMI XAMD LXY 13 13 13 XAM XAMI XAMD LXY 14 14 14 XAM XAMI XAMD LXY 15 15 15
TAMR IAP2 TAB3 SNZT3 TAI1
IAP3 TAB4 SNZT4 SVDE - - - TABPS - - TABSI TABAD - - - - - - - - - - - -
TQ1A TK1A TQ2A TK2A
TAQ1 TAI2 -
TPSAB TAQ2 - T4HAB
TQ3A TMRA OP6A - - TRGA - - - - TW1A TW2A TI1A -
TAQ3 TAK0 IAP6 - - TAPU0 - - - - - - - - - -
SNZAD T4R4L - - - - - -
TI2A TFR0A TSIAB - - TK0A - - - -
TFR1ATADAB TALA TAK1 TFR2A - - TPU0A TPU1A - - - TAK2 - - -
CMCK TPAA CRCK - - - - -
TR3AB TAW1 - - - TAW2 TAW3
RCP DWDT SCP CYCK - - - ADST
TAW4 TAPU1 -
TR1AB TAW5
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011
BL BML BLA BMLA SEA SZD
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, P3, P6, D0-D6, RESET, XIN, VDCE Input voltage CNTR0, CNTR1, INT0, INT1 Input voltage AIN0, AIN1 Output voltage P0, P1, P2, P3, P6, D0-D6, RESET, C Output voltage CNTR0, CNTR1 Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Conditions Ratings -0.3 to 6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 -20 to 85 -40 to 125 Unit V V V V V V V mW C C
Output transistors in cut-off state Output transistors in cut-off state Ta = 25 C 32P6U-A
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (when ceramic resonator/on-chip oscillator is used) Conditions Mask ROM version f(STCK) 6 MHz f(STCK) 4.4 MHz f(STCK) 2.2 MHz f(STCK) 1.1 MHz One Time PROM version f(STCK) 6 MHz f(STCK) 4.4 MHz f(STCK) 2.2 MHz VDD VDD VRAM VSS VIH VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOH(avg) IOH(avg) IOL(peak) IOL(peak) IOL(peak) IOL(avg) IOL(avg) IOL(avg) IOH(avg) IOL(avg) Supply voltage (when RC oscillation is used) Supply voltage (when quartz-crystal oscillator is used) RAM back-up voltage Supply voltage "H" level input voltage "H" level input voltage "H" level input voltage "L" level input voltage "L" level input voltage "L" level input voltage "H" level peak output current "H" level peak output current "H" level average output current (Note) "H" level average output current (Note) "L" level peak output current "L" level peak output current "L" level peak output current "L" level average output current (Note) "L" level average output current (Note) "L" level average output current (Note) "H" level total average current "L" level total average current D0-D6, C CNTR0, CNTR1 P0, P1, P2, P6 P3, RESET D0-D6, C CNTR0, CNTR1 P0, P1, P2, P6 P3, RESET P0, P1, P2, P3, P6, D0-D6, VDCE, XIN
RESET
Limits Min. 4.0 2.7 2.0 1.8 4.0 2.7 2.5 2.7 2.0 2.5 1.6 2.0 0 0.8VDD 0.85VDD 0.85VDD 0 0 0 VDD VDD VDD 0.2VDD 0.3VDD 0.15VDD -20 -10 -30 -15 -10 -5 -20 -10 24 12 10 4 24 12 12 6 5 2 15 7 -60 -60 80 80 Typ. Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Unit V
f(STCK) 4.4 MHz Mask ROM version One Time PROM version Mask ROM version f(XIN) 50 kHz f(XIN) 50 kHz
V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA
at RAM back-up mode One Time PROM version at RAM back-up mode
CNTR0, CNTR1, INT0, INT1 P0, P1, P2, P3, P6, D0-D6, VDCE, XIN
RESET
CNTR0, CNTR1, INT0, INT1 VDD = 5 V P0, P1, D0-D6 CNTR0 C, CNTR1 P0, P1, D0-D6 CNTR0 C, CNTR1 VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V
D0-D6, C, CNTR0, CNTR1 P0, P1 P2, D0-D6, RESET, CNTR0, CNTR1 P0, P1, P3, P6
Note: The average output current is the average value during 100 ms.
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Mask ROM version Conditions Through mode VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/4, 8 mode VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V One Time PROM Through mode version VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Limits Typ. Max. 6.0 4.4 2.2 1.1 6.0 4.4 2.2 6.0 4.4 6.0 4.4 2.2 6.0 4.4 6.0 4.4 VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V Frequency/4, 8 mode VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V One Time PROM Through mode version VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/4, 8 mode VDD = 2.5 to 5.5 V
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
When ceramic resonance is used f(STCK) [MHz] 6 When RC oscillation is used f(STCK) [MHz] When external clock is used f(STCK) [MHz]
Min.
Unit MHz
VDD = 2.5 to 5.5 V Frequency/2 mode VDD = 2.7 to 5.5 V VDD = 2.5 to 5.5 V Frequency/4, 8 mode VDD = 2.5 to 5.5 V f(XIN) f(XIN) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic resonator selected, external clock input) Mask ROM version Through mode VDD = 2.7 to 5.5 V
MHz MHz
4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8 3.2 1.6 4.8 3.2 4.8
4.8 4.4 4.4
3.2 2.2
Recommended operating operation
Recommended operating operation
1.6
Recommended operating operation
1.1 0.8 VDD[V] VDD[V] 1.8 2 2.7 (2.5) 4 5.5 VDD
1.8 2 2.7 (2.5)
4
5.5
2.7
5.5
( ): One Time PROM version
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
RECOMMENDED OPERATING CONDITIONS 3
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a quartz-crystal oscillator) f(CNTR) Timer external input frequency tw(CNTR) Timer external input period TPON ("H" and "L" pulse width) Power-on reset circuit valid supply voltage rising time Mask ROM version One Time PROM version CNTR0, CNTR1 CNTR0, CNTR1 Mask ROM version One Time PROM version VDD = 0 1.8 V VDD = 0 2.5 V Conditions VDD = 2.0 to 5.5 V VDD = 2.5 to 5.5 V 3/f(STCK) 100 100 Limits Typ. Unit kHz
Min.
Max. 50 50
f(STCK)/6 Hz s s
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS 1
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VOH Parameter "H" level output voltage P0, P1, D0-D6, CNTR0 VDD = 3 V VOH "H" level output voltage C, CNTR1 VDD = 3 V VOL "L" level output voltage P0, P1, P2, P6 VDD = 3 V VOL "L" level output voltage P3, RESET VOL "L" level output voltage D0-D6, C, CNTR0, CNTR1 VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V IIH "H" level input current P0, P1, P2, P3, P6, D0-D6, VDCE, RESET, CNTR0, CNTR1, INT0, INT1 IIL "L" level input current P0, P1, P2, P3, P6, D0-D6, VDCE, CNTR0, CNTR1, INT0, INT1 RPU Pull-up resistor value VI = 0 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V Mask ROM version f(XIN) Frequency error (with RC oscillation, error of external R, C not included ) (Note)
Note: When RC oscillation is used, use the external 30 or 33 pF capacitor (C).
Test conditions VDD = 5 V IOH = -10 mA IOH = -3 mA IOH = -5 mA IOH = -1 mA IOH = -20 mA IOH = -6 mA IOH = -10 mA IOH = -3 mA VDD = 5 V IOL = 12 mA IOL = 4 mA IOL = 6 mA IOL = 2 mA IOL = 5 mA IOL = 1 mA IOL = 2 mA IOL = 15 mA IOL = 5 mA IOL = 9 mA IOL = 3 mA VI = VDD Port P6 selected
Limits Min. 3 4.1 2.1 2.4 3 4.1 2.1 2.4 2 0.9 0.9 0.6 2 0.9 0.9 2 0.9 1.4 0.9 2 Typ. Max.
Unit V
VDD = 5 V
V
V
V
V
A
VI = 0 V P0, P1 No pull-up Port P6 selected
-2
A
VDD = 5 V VDD = 3 V
30 50
P0, P1, RESET VT+ - VT- Hysteresis CNTR0, CNTR1, INT0, INT1 VT+ - VT- Hysteresis RESET f(RING) On-chip oscillator clock frequency
60 120 0.2 0.2 1 0.4
125 250
k V V
200 100 VDD = 1.8 V 30
500 250 120
700 400 200 17 17
kHz
VDD = 5 V 10 %, Ta = 25 C VDD = 3 V 10 %, Ta = 25 C
% %
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS 2
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol IDD Parameter Supply current at active mode on-chip oscillator stop) VDD = 5 V f(XIN) = 4 MHz VDD = 5 V Test conditions f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) VDD = 3 V f(XIN) = 4 MHz f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 at active mode (with a quartz-crystal oscillator, on-chip oscillator stop) VDD = 3 V f(XIN) = 32 kHz VDD = 5 V f(XIN) = 32 kHz f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) VDD = 5 V at active mode (with an on-chip oscillator, f(XIN) stop) VDD = 3 V f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) at RAM back-up mode (POF instruction execution) Ta = 25 C VDD = 5 V VDD = 3 V Limits Min. Typ. 1.4 1.6 2.0 2.8 1.1 1.2 1.5 2.0 0.4 0.5 0.6 0.8 55 60 65 70 12 13 14 15 50 70 100 150 10 15 20 35 0.1 Max. 2.8 3.2 4.0 5.6 2.2 2.4 3.0 4.0 0.8 1.0 1.2 1.6 110 120 130 140 24 26 28 30 100 140 200 300 20 30 40 70 3 10 6 mA mA Unit mA
(with a ceramic resonator, f(XIN) = 6 MHz
A
A
A
A
A
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
A/D CONVERTER RECOMMENDED OPERATING CONDITIONS
(Comparator mode included, Ta = -20 C to 85 C, unless otherwise noted) Symbol VDD VIA f(ADCK) Parameter Supply voltage Analog input voltage A/D conversion clock frequency (Note) One Time PROM version Note: Definition of A/D conversion clock (ADCK) Mask ROM version VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V VDD = 2.0 to 5.5 V VDD = 4.0 to 5.5 V VDD = 3.0 to 5.5 V Conditions Mask ROM version One Time PROM version Limits Typ. Unit V V kHz
Min. 2.0 3.0 0 0.8 0.8 0.8 0.8 0.8 0.8
Max. 5.5 5.5 VDD 334 245 3.9 1.8 334 123
On-chip oscillator clock (RING) Division circuit Divided by 8 On-chip oscillator Ceramic resonance Divided by 4 MR0 1 Multiplexer (CMCK, CRCK, CYCK) Division circuit Divided by 48 Q32 Instruction clock (INSTCK) On-chip oscillator clock(RING) 0 1 Divided by 24 Divided by 12 Divided by 6 Q31, Q30 11 10 01 00 A/D conversion clock (ADCK) 0 Divided by 2 MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3) System clock (STCK)
Instruction clock (INSTCK)
XIN
RC oscillation Quartz-crystal oscillation

f(ADCK) [kHz] 334
245 (123)
Recommended operating operation
3.9 (15.3) 1.8 0.8 2 2.2 2.7 (3.0) ( ): One Time PROM version 4 5.5 VDD[V]
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
A/D CONVERTER CHARACTERISTICS
(Ta = -20 C to 85 C, unless otherwise noted) Symbol - - - V0T Parameter Resolution Linearity error 2.7 (3.0) V VDD 5.5 V ((): One Time PROM version) Mask ROM version 2.2 V VDD < 2.7 V 0 0 0 0 3 5105 3064.5 2552.5 5100 3065 10 7.5 7.5 15 13 5115 3072 2560 5115 3075 Test conditions Min. Limits Typ. Max. 10 2 4 0.9 20 15 15 30 23 5125 3079.5 2567.5 5130 3085 8 150 75 450 225 31 LSB A mV Unit bits LSB LSB mV
Differential non-linearity error 2.2 (3.0) V VDD 5.5 V ((): One Time PROM version) VDD = 5.12 V Mask ROM version Zero transition voltage VDD = 3.072 V VDD = 2.56 V One Time PROM version VDD = 5.12 V VDD = 3.072 V VDD = 5.12 V VDD = 3.072 V One Time PROM version VDD = 2.56 V VDD = 5.12 V VDD = 3.072 V 2.0 V VDD < 2.2 V
VFST
Full-scale transition voltage
Mask ROM version
- IADD TCONV
Absolute accuracy (Quantization error excluded) A/D operating current (Note 1) A/D conversion time
Mask ROM version VDD = 5 V VDD = 3 V f(XIN) = 6 MHz
s
f(STCK) = f(XIN) (XIN through mode) ADCK=INSTCK/6 - - Comparator resolution Comparator error (Note 2) Mask ROM version VDD = 5.12 V VDD = 3.072 V VDD = 2.56 V One Time PROM version - VDD = 5.12 V VDD = 3.072 V Comparator comparison time f(XIN) = 6 MHz f(STCK) = f(XIN) (XIN through mode) ADCK=INSTCK/6
Notes 1: When the A/D converter is used, IADD is added to IDD (supply current). 2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
8 20 15 15 30 23 4
bits mV
s
Logic value of comparison voltage Vref Vref = VDD 256 n
n = Value of register AD (n = 0 to 255)
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = -20 C to 85 C, unless otherwise noted) Symbol VRST- VRST+ VRST+ - VRST- IRST TRST Operation current (Note 3) Detection time VDD = 5 V VDD = 3 V VDD (VRST- - 0.1 V) (Note 4) 50 30 0.2 100 60 1.2 Parameter Detection voltage (reset occurs) (Note 1) Detection voltage (reset release) (Note 2) Detection voltage hysteresis Ta = 25 C Ta = 25 C Test conditions Min. 1.4 1.1 1.5 1.2 0.1 Limits Typ. 1.5 1.6 Max. 1.6 1.9 1.7 2.0 V Unit V V
A
ms
Notes 1: The detected voltage (VRST-) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. 2: The detected voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. 3: When the voltage drop detection circuit is used (VDCE pin = "H"), IRST is added to IDD (power current). 4: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- - 0.1 V].
BASIC TIMING DIAGRAM
Machine cycle
Parameter
Pin (signal) name
Mi
Mi+1
System clock
STCK
Port D output
D0-D6
Port D input
D0-D6
Ports P0, P1, P2, P3, P00-P03 P10-P13 P6 output P20-P23 P30, P31 P60-P63
Ports P0, P1, P2, P3, P00-P03 P10-P13 P6 input P20-P23 P30, P31 P60-P63
Interrupt input
INT0, INT1
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4583 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 21 shows the product of built-in PROM version. Figure 69 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Table 21 Product of built-in PROM version PROM size Part number ( 10 bits) M34583EDFP 16384 words
RAM size ( 4 bits) 384 words
Package 32P6U-A
ROM type One Time PROM [shipped in blank]
PIN CONFIGURATION (TOP VIEW)
24
23
22
21
20
19
18
17 16 15 14
P03 P10 P11 P12 P13 D0 D1 D2
P31/INT1
P61/AIN1
P60/AIN0
P02
P01
P00
P63
P62
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
P30/INT0 VDCE VDD VSS XIN XOUT CNVSS RESET
M34583EDFP
13 12 11 10 9
D6/CNTR0
C/CNTR1
P20
P21
Fig. 69 Pin configuration of built-in PROM version
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
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P22
D3
D4
D5
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
(1) PROM mode
The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapter is listed in Table 22. Contact addresses at the end of this data sheet for the appropriate PROM programmer. * Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 70.
Table 22 Programming adapter Microcomputer Name of Programming Adapter M34583EDFP PCA7442FP
Address 000016
1
1
1
D4 D3
D2
D1
D0
Low-order 5 bits
(2) Notes on handling
A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. For the One Time PROM version shipped in blank, Renesas Technology Corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 71 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped).
3FFF16 400016
1
1
1
D4 D3
D2
D1
D0
High-order 5 bits
7FFF16
Fig. 70 PROM memory map
(3) E l e c t r i c C h a r a c t e r i s t i c D i f f e r e n c e s Between Mask ROM and One Time PROM Version MCU
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version.
Writing with PROM programmer
Screening (Leave at 150 C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 C exceeding 100 hours.
Fig. 71 Flow of writing and test of the product shipped in blank
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 150 of 151
PRELIMINARY
4583 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
PACKAGE OUTLINE
32P6U-A
Recommended
JEDEC Code - HD D
32 25
Plastic 32pin 77mm body LQFP
Weight(g) Lead Material Cu Alloy e MD
EIAJ Package Code LQFP32-P-0707-0.80
I2
1 24
Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
8
17
9
16
E HE
A
L1 A2
A3
e
F
A1
L
Lp
b
c
x y b2 I2 MD ME
x
M
y
Detail F
Rev.3.00 Aug 06, 2004 REJ03B0009-0300Z
page 151 of 151
b2
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.32 0.37 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 - 0.8 - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.75 0.6 0.45 - 0.25 - - - 0.2 0.1 - - 0 10 - 0.5 - - 1.0 - - 7.4 - - - - 7.4
ME
REVISION HISTORY
Rev. Date Page -
4583 GROUP DATA SHEET
Description Summary
1.00 Feb. 18, 2003 2.00 Apr. 15, 2003
First edition issued Some values of the following table are revised. RECOMMENDED OPERATING CONDITIONS 1; 141 * Supply voltage (when quartz-crystal oscillator is used) * RAM back voltage 143 RECOMMENDED OPERATING CONDITIONS 3; * Oscillation frequency (with a quartz-crystal oscillator) 147 A/D CONVERTER RECOMMENDED OPERATING CONDITIONS; * Supply voltage * A/D conversion clock frequency 148 A/D CONVERTER CHARACTERISTCS; * Linearity error * Differential non-linearity error * Zero transition voltage * Full-scale transition voltage * Comparator error 2.01 Sep.16, 2003 14 Port block diagram (7): Period measurement mode added. 24 Fig.17: Period measurement mode added. 38 (12) PWM output function (C/CNTR1, timer 3, timer 4) revised. 39 (14) Precautions: Timer 4 revised. 52 Fig.42: SRST instruction added . 55 Note on voltage drop detection circuit added. 56 Table 16 Port level revised. 65 LIST OF PRECAUTIONS: Timer 4 revised. 69 LIST OF PRECAUTIONS: Note on voltage drop detection circuit added. 3.00 Aug.06, 2004 All pages Words standardized: On-chip oscillator, A/D converter ____________ 4 Description of RESET pin revised. 32 Fig.26 : Note 7 added. 37 Some description revised. 43 Some description revised. 44 Fig.33 : "DI" instruction added. 70 Note on Power Source Voltage added. 71 Note 2 : revised.
(1/1)
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c)2003, 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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